ContributionsMost RecentMost LikesSolutionsSource Synchronous Interface Output Constraint Hi, I am trying to write timing constraints for FPGA - SDRAM communications. I know as per Intel documentation, the formulas are: output maximum delay = maximum trace delay for data + tSU of external register - minimum trace delay for clock output minimum delay = minimum trace delay for data – tH of external register - maximum trace delay for clock Now, For my design I have the maximum & minimum trace delays from PCB design of the board (considering 16 data lines between FPGA & SDRAM. I also have the tSU from SDRAM data sheet. My questions are: 1) To calculate the board delay, I looked at the data (D0-D15) trace length between FPGA & SDRAM, using the PCB designer tool. Using the trace length and other parameters, I calculated the min & max board delay between FPGA and SDRAM. Is that the right way of doing it? 2) How can I calculate the minimum & maximum trace delay for the clock? There is only (clock) line going from FPGA to SDRAM, so it will have only 1 delay value. How do I calculate min and max for the clock trace? Please advise Thanks Sahil Re: Questa lpm CycloneV library not found I am using Quartus Prime Standard 20.1.1 I am also using Questa-Intel FPGA Edition 2022.1 (Quartus Prime Pro 22.2). I changed the Questa-Intel FPGA Edition to 21.1 (Standard). It works now. Thanks a lot for your help. Questa lpm CycloneV library not found Hi, I have been using Quartus Prime Standard & Altera-Modelsim software for my design on cycloneV FPGA device for couple of years now. Last week I installed Questa Intel software to replace the Modelsim software. All the rtl files compile fine, except one lpm IP module. When I try to compile that lpm IP module, it generates an error: "(vcom-1598) Library "cyclonev" not found". (screenshot below) I am not sure why that error is getting generated. Do I need to install any additional cycloneV device packages for the Questa software? Or are there any packages that I need to move from Modelsim to Questa? Kindly help! Thanks Re: How to setup Questa Sim license file Not received any message. Inbox is empty. Re: How to setup Questa Sim license file License.dat file: (Attached in zip file) Name : Sahil Bhat Email Address : Sahil.Bhat@Honeywell.com Company Name : Honeywell Company Address : 2101 City West Blvd Houston TX 77042 NICID(Mac Add) : 98-E7-43-7A-1A-AE Re: How to setup Questa Sim license file I am having the exact same issue. I changed the Environment Variables as per instructions but still having same problems. Questa Starte License Renewal Hi, I understand that Questa-Intel FPGA Starter edition needs a license which is free for a year. My question is when I apply for license renewal next year, do I have to pay the license fee then or is the renewal license free as well? Thanks Quartus Prime Floating License with Standalone Modelsim License I am using Quartus Prime Std floating license and Intel- Modelsim floating license. My question is Can I use Quartus Prime Std floating license with Intel_Modelsim Standalone license? Will be there be any issues with this configuration? Please advise! Thanks Re: Quartus Prime Floating License Renewal Invalid LAC Thanks. But I don't think ITorder people have any idea on how to renew the license. Can you please send me a document or a link that I can share with them, that'd help them to execute the renewal process. Thanks Re: Quartus Prime Floating License Renewal Invalid LAC That is right. itorderfulfillment@honeywell.com is the Honeywell IT team who procured the license renewal on my request. But Still I am the user. Kindly advise what the next steps should be. I really need the license to renewed as soon as possible. Thanks