ContributionsMost RecentMost LikesSolutionsArria 10 FPGA Development Kit DDR3 characteristics Hello, UG-20007 indicates that the DDR3L on the HILO daughter board is 5x MT41K512M16TNA-107. However, when using the preset ("ARRIA 10 GX FPGA Development Kit with DDR3 HILO") to generate an EMIF example design, the component seems to be MT41K256M8TNA-093 (tFAW = 25, row address width = 15, memory clock frequency = 1066.667). This is based on Q Prime Pro 20.2. Does someone know what the correct information is? I currently don't have access to a devkit to check the devices themselves. Thanks! Re: Is it possible to archive snapshots? @KennyTan_Altera , Sorry for the delay. I had lost track of this and the notifications were in my spam. Given that test_ram only contains test_rd_ram.ip I don't understand what you mean by "can you try to use include at the top of your .v/vhdl files to include the necessary files?" Re: Is it possible to archive snapshots? Sorry, hereby the corrected qar. Re: Is it possible to archive snapshots? @KennyTan_Altera I made a small design based on a simple Intel IP (RAM) and I get the exact same behavior. The archive is attached. Re: Is it possible to archive snapshots? @KennyTan_Altera Sorry for the delay. The design does include DDR. These are proprietary files which I cannot share in this forum. Re: Is it possible to archive snapshots? @KennyTan_Altera Thanks for the suggestion. I tried to follow "1.5.2. Reusing Root Partitions". However, I don't do the steps described in 1.5.2.1 and 1.5.2.2 as my objective is not to create a root_partition with the peripherals and a reserved space for future use (see my previous post). As per 1.5.2.3 the fitter completes but then I get the same error as in my initial post when I try the second step: 'No partitions are available for export.' Re: Determine source files effectively used in project @KhaiChein_Y_Intel Thanks for the feedback! It's a pity that this information is no longer available. Jorva Determine source files effectively used in project Hello, Due to reuse of existing IP, not all files read by quartus are necessary. Is it possible to list which files are not used? The synthesis source files read report doc seems to indicate that it includes this information but in QII Pro 20.2 I cannot find it. Thanks! SolvedRe: Is it possible to archive snapshots? An update: The qdb files are effectively generated using the commands design::export_partition root_partition -snapshot synthesized -file post_synth.qdb design::export_partition root_partition -snapshot final -file post_fit.qdb However, I don't see how I can import this qdb. When I assign it to the root_partition of the archived project, analysis & elaboration gives the following error: Error(19829): ../../../../quartus/post_fit.qdb cannot be assigned. The ../../../../quartus/post_fit.qdb file is missing Partial Reconfiguration or Reserved Core subpartitions and assigned to the root partition. In order to assign a QDB file to the root partition, it must be created from a design using Partial Reconfiguration or Reserved Core subpartitions. To correct this error, ensure that the creation and assignment of the QDB is correct. To restate my original objectives. I would like to : 1) retain a reasonably sized database of a completed implementation which, at a later date, can be reopened (without re-running the implementation) to be further analyzed (timings, placement, etc). 2) analyze an intermediate snapshot while the (scripted) implementation is not yet complete. Maybe the snapshot is not the ideal method to go about this? As a comparison, Vivado allows this with the design checkpoints. Re: Is it possible to archive snapshots? Just saw the following explanation for the error: Error(18895): The TCL command design::export_partition from the design package is not supported while running on the Quartus Graphical User Interface The idea is to do it using scripting anyways so I'll try that.