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Re: HAL API for the Generic Serial Flash Interface FPGA IP, 'altera_safeclib'
It was the same problem as what I described (community.intel.com/t5/Nios-II-Embedded-Design-Suite/HAL-API-for-the-Generic-Serial-Flash-Interface-FPGA-IP-altera/m-p/1393376#M51250). Can we arrange a call to discuss?1.7KViews0likes1CommentRe: HAL API for the Generic Serial Flash Interface FPGA IP, 'altera_safeclib'
Hi Hareesh, Thank you for sharing the source files, that's very helpful. However, it would really help me to understand why my Quartus 21.1 install is behaving as it is. I requested a remote session in a previous ticket and I'd be happy to go ahead with this if you can arrange it. Thanks Meenal4.9KViews0likes3CommentsRe: HAL API for the Generic Serial Flash Interface FPGA IP, 'altera_safeclib'
@hareesh Are there special licensing requirements for the Generic Serial Flash Interface IP? I have tried this on a different machine with no luck. I really only want the source files for information purposes. Would you be able to zip and send these to me via email?5KViews0likes6CommentsRe: HAL API for the Generic Serial Flash Interface FPGA IP, 'altera_safeclib'
Hi @hareesh , I've attached the .qsys and the .sopcinfo. I don't know if this is relevant but the IP cores were originally from a Quartus Prime 18.1 design and have been upgraded by the tool to 21.1. Thanks.5KViews0likes9Comments