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lambert_yu
Joined 6 years ago
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Re: How to manual control the E-Tile transceiver's CDR mode of agilex 7
Hi, Thanks for your response. Now we have requirement for CDR's working mode for special high speed protocol. From your information, If we want to control CDR's working mode more precisely, there's no any work around solution, right? That means we need to change to other FPGA chip? Best Regards, Lambert37Views0likes1CommentHow to manual control the E-Tile transceiver's CDR mode of agilex 7
Hi, fpga chip : AGFB014R24B2E3VNL Issue : rx_set_locktodat and rx_set_locktoref doesn't present in E-Tile's Transceiver's CDR, and I didn't found the related avalon register to control this part in the E-Tile Transceiver PHY user guide Does E-Tile transceiver support this feature in Agilex 7 Device? If so, could you please share this part information? Best Regards, LambertSolved119Views0likes5CommentsRe: dynamic configuration issue of fpll from arria 10
Hi, I am so sorry that I have limited authority that I could not transfer our design to you. But for the fpll design, I could provide the related configuration : And I think this information could help to generate the related IP. About dynamic logic, maybe you need to re-design.207Views0likes0CommentsRe: dynamic configuration issue of fpll from arria 10
Hi, Just because I could not send our project to you(I have limited authority). I could only present my implementation step. 1. Configure fpll to one default frequency; 2. During simulation, use fixed M count, and continue to adjust K count. (gap about 800 us). Use same N and C0 count; For the dynamic configuration: 1. configure C0; 2. configure M 3, configure N; 4. configure K 5. power down to do reset and re-calibration Or maybe could you help provide one example, and I could try it at my side, thanks Best Regards331Views0likes0CommentsRe: dynamic configuration issue of fpll from arria 10
I made sure I have written all register correctly through reading the related register after write. And I found that 1st k value, 2ed k value has same frequency; 3rd value, 4th value has another same frequency; 1st and 2ed k value is diff; 3rd value and 4th value is diff. Update frequency is 861us.522Views0likes0Commentsdynamic configuration issue of fpll from arria 10
Hi, all quartus ip : quartus 191 IP : fpll operation mode : fraction mode For change the frequency of fpll: I modify c0/m/n/k, after configure these register , then use register to reset and re-calibrate fpll. I found that:(during simulation) 1) if there's no m change, though k value is changed, the fpll could not synthesis the new frequency; workaround : I must change m to another value then change it back, then update k value; the fpll could synthesis the new frequency; I don't know why. it's so strange. 2) Though there's workaround solution, but I found that sometimes, previous and current k value has large difference(for example ,previous value is 32'h98dbc000 , current value is 32'h5b110000), but the fpll could not provide correct frequency. How could I resolve this issue? Or which way will I need to try? Best Regards, Lambert653Views0likes11Comments