skyjuice
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Re: Is Agilex Synthesis is Timing Driven ?
If you go to Quartus Settings --> Compiler Settings you will find a description of what each optimization mode does. The superior mode make changes to the synthesis stage to target better performance. Hope that answers your questions.736Views0likes0CommentsRe: Very high interconnect delay
The design has such a high interconnect delay is due to the huge clock skew. In order to meet hold time requirement, the router will need to add additional routing delays. Why huge clock skew you might ask? That's because this is a cross-clock transfer.1.3KViews1like1CommentRe: How to reduce IC delay? Useful resources
I saw that there are only 2 logic levels which are not huge. The IC delay is likely due to the source and destination nodes being placed far away. As a start, are there a lot of fanouts from the source nodes or the combination logic? Or could there be some sort of nodes beyond this path that is pulling them in opposite direction (if you know what I mean)3.2KViews0likes0CommentsRe: Change clock propagation through multiplexers
Think of it this way - I have 2 inputs to a mux (clkA and clkB), and you're right only one clock will be selected. Let's assume for a specific scenario, clkA is selected and somewhere in the the downstream logic, it will need to perform a transfer to clkB and this will need to be timing-analyzed. If the tool where to cut all clkA <--> clkB paths, then the mentioned path will be affected, which is not what we want.3.1KViews0likes3CommentsRe: Controlling skew between clocks
Thanks for the info. As expected, these are cross-clock transfers causing the huge clock skew. I suspect that the clock buffer for one of those clock networks must be located far away. You can see this through the timing report in Timing Analyzer (compare between Clock Arrival and Clock Required) and then locate them in Chip Planner for visualization. Can you try putting them into the clock networks whose the buffers are close to each other?1.5KViews0likes0Comments