Video Demo: Designing Broadcast Video Equipment Using SDI
Intel has just published a video with an SDI demo implemented with an Intel Agilex I-Series FPGA and the SDI II IP core. The demo is based on an SDI retransmit design that does not require an external VCXO for genlocking purposes. Instead, it uses the Intel Agilex I-Series FPGA’s internal transmit phase-locked loop (PLL) on the FPGA’s F-tile in fractional mode.