IEEE 802.1 TSN IP and software from TTTech Industrial now available packaged with selected Cyclone® V SoC FPGAs
Time Sensitive Networking (TSN) is the IEEE 802.1 standard for deterministic packet transmission and handling over Ethernet networks. It is a set of evolving IEEE standards that support a mix of deterministic, real-time and best-effort traffic over fast Ethernet connections; provides precise time synchronization of network nodes using synchronized, distributed local clocks; and serves as the network foundation for smart factories, Industry 4.0, and Intelligent Internet of Things (IIoT) applications. Intel is now offering special TSN versions of three Cyclone® V SoC FPGAs that include TTTech Industrial’s TSN Edge IP Solution with both an IP core and the embedded software required to build a TSN switch. There are no up-front license fees, no per-unit royalty reporting, and no protracted negotiations for the TTTech Industrial IP or software when the Cyclone V SoC FPGAs are purchased through Intel or its authorized distributors. Three Cyclone V SoC FPGAs are available packaged with the TTTech Industrial TSN Edge IP solution: Cyclone V SE SoC FPGA, U484 package (19mm), OPN: 5CSEBA6U19I7NTS Cyclone V SE SoC FPGA, U672 package (23mm), OPN: 5CSEBA6U23I7NTS Cyclone V SX SoC FPGA, U672 package (23mm), OPN: 5CSXFC6C6U23I7NTS For more details including ordering instructions, click here. For more information on implementing and using TSN in Intel FPGAs, see “Time Sensitive Networking: From Theory to Implementation in Industrial Automation.” Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices and Disclaimers Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.FPGA-Based Cloaking and Security Tech Helps Protect Equipment on IT and OT Networks from the Bad Guys
You can’t attack what you can’t see, and cloaking technology for devices on Ethernet LANs is merely one of many protection layers implemented in Q-Net Security’s Q-Box to protect networked devices and transaction between these devices from cyberattacks. Other security technologies built into the Q-Box include encryption, authentication, and the use of different, randomly generated security keys created just in time for each transaction – called JITKeys – with no external key management. Adding security to a networked device is as simple as placing a small Q-Box between a protected device and its LAN using an extra RJ45 cable. Each Q-Box can protect as many as 2000 network endpoints, allowing operators to create protected LAN segments throughout a larger network. Connect the Q-Box to a WAN router and the protected LAN segments can be located anywhere in the world. You can use the Q-Box to protect a wide range of networked devices including: Servers and PCs on IT networks Financial equipment ranging from ATMs in banks to slot machines in casinos Equipment connected to Operational Technology (OT) networks in buildings, factories, refineries, and utilities including PLCs and other industrial controllers, lighting systems, security systems and cameras, and even robotic equipment The Q-Box can secure any device on an Ethernet LAN. The Q-Box works with all networked devices including legacy systems. Face it. Cyberspace is getting more dangerous every day. Need proof? Here are just a handful of recent cyberattacks: December, 2020: Hackers inserted malicious code into SolarWinds’ Orion software, exposing sensitive and critical data at top government agencies including parts of the Pentagon, the Department of Homeland Security, the State Department, the Department of Energy, the National Nuclear Security Administration, and the Treasury; corporations including systems Microsoft, Cisco, Intel, and Deloitte; and other organizations including the California Department of State Hospitals, and Kent State University. 1 February, 2021: A Hacker attempted to poison the drinking water supply for Oldsmar, Florida by dangerously increasing sodium hydroxide levels in the water. 2 March, 2021: Hackers compromised more than 150,000 security cameras located in gyms, jails, schools, hospitals, and factories. 3 May, 2021: The DarkSide Russian hacking group forced Colonial Pipeline to cut the connection between its IT and OT networks, shutting down the company’s 5500-mile pipeline for several days and causing massive gasoline shortages on the US east coast. 4 Q-Net implemented the secure technology inside of the Q-Box using the programmable hardware in an Intel® Cyclone® FPGA. The Q-Box provides access protection without requiring changes or additions to an endpoint’s legacy code and with no modifications to existing equipment. In addition, the FPGA-based hardware in the Q-Box does not require and does not permit software updates or patches from the network. The network security protection it supplies is immutable. Because it’s implemented in hardware on an FPGA, the Q-Box introduces only a few microseconds of network latency. For more information about Q-Net Security’s Q-Box, click here. Notices and Disclaimers “SolarWinds Hack Victims: From Tech Companies to a Hospital and University,” The Wall Street Journal, https://www.wsj.com/articles/solarwinds-hack-victims-from-tech-companies-to-a-hospital-and-university-11608548402 “A Hacker Tried to Poison a Florida City's Water Supply, Officials Say,” Wired, https://www.wired.com/story/oldsmar-florida-water-utility-hack/ “Hackers just pulled off one of the most mind-boggling hacks of 2021 so far,” BGR Media, https://bgr.com/tech/security-cameras-hacked-verkada-customers-exposed/ “Intel® Agilex® FPGAs target IPUs, SmartNICs, and 5G Networks,” https://www.intel.com/content/dam/www/central-libraries/us/en/documents/agilex-fpgas-target-ipus-smartnics-5g-networks-white-paper.pdf Intel technologies may require enabled hardware, software or service activation. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
Accelerate NFVi Workloads For 5G Deployments Webinar: Watch On-Demand Now
The recently-held “Accelerate NFVi Workloads For 5G Deployments” webinar highlights the collaboration between Juniper Networks, HCL Technologies, and Intel® to solve network performance challenges and allow Contrail users to experience increased overall server performance and utilization for vRouter-based infrastructures in telecommunications environments.Open vSwitch for NFVi based on Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 achieves first-packet learning rate of 500K rules/sec, near-wireline performance
As the numbers of subscribers, competitors, and technology advances grow, communications service providers (CoSPs) need to differentiate their products and services while keeping improved power efficiency and the need to control total cost of ownership (TCO) as ever-present goals. Intel and HCL have addressed these challenges with a joint solution that combines Intel® hardware and HCL software. HCL has created a solution using the Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 that can dramatically increase network functions virtualization infrastructure (NFVi) routing and switching performance while preserving flexibility. The resulting solution, the Open vSwitch (OvS), is a production quality, multilayer virtual switch that can implement software-defined networking (SDN), which is crucial to creating a closed-loop, fully automated NFVi solution. The OvS can either forward packets through a kernel-based datapath or by using the Linux Data Plane Development Kit (DPDK). Aggressive software optimization offloads NFVi forwarding tasks to the Intel FPGA PAC N3000, yielding the following preliminary results 1 : For more details, see the new Solution Brief titled “Increase NFVi Performance and Flexibility.” (Click on the link to download the Solution Brief.) Notices and Disclaimers 1 Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at intc.com. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Hardware Acceleration and Segment Routing over IPv6 (SRv6) help CoSPs Optimize and Simplify their Networks
Communications service providers (CoSPs) are seeking ways to differentiate themselves and to enhance their customers’ experiences in the fast-evolving telecommunication (telco) market—all while keeping costs under control. Exponential traffic growth and constant pressure to add more services and subscribers can tax legacy infrastructure, forcing CoSPs to constantly optimize and simplify their networks. Many CoSPs have deployed network functions virtualization (NFV) in an effort to optimize their networks. However, an influx of new subscribers and growing data loads consume a growing number of CPU cycles simply to route traffic, which leaves fewer compute resources to run actual containerized network functions (CNFs) and virtualized network functions (VNFs) that CoSPs want to support. The end result: suboptimal performance and the need for more hosts. To help overcome these challenges, CoSPs are turning to technologies such as hardware acceleration and segment routing over IPv6 (SRv6). SRv6 helps address the requirements of NFV and software-defined networking (SDN) architecture. It provides a unified solution for networking programmability, service function chaining (SFC), protocol simplification, traffic engineering, and mobile and fixed network convergence. An SRv6 solution from Intel and HCL overcomes network bottlenecks and achieves up to 3x savings in processor cores by offloading low-level SRv6 processing to the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000. The card is reprogrammable and delivers the flexibility that CoSPs need to support new networking workloads. HCL has built an optimized architecture that enhances network throughput and predictability while reducing latency by taking advantage of the plugin-based framework of vector packet processing (VPP) and by offloading CPU-intensive operations to the Intel FPGA PAC N3000. The solution frees up CPU cores by offloading CPU-intensive segment-routing functions to the Intel FPGA PAC N3000, which means that four CPU cores in the hardware-assisted solution can deliver comparable performance to 12 cores running a software-based SRv6. That’s a 3x savings in CPU cores as shown in the graphic below. 1 Freed CPU cores and cycles can be dedicated to vital CNF workloads running on that networking infrastructure instead of networking infrastructure. The solution’s small footprint can help reduce power and cooling costs. It is available for both VNF-based environments through VPP support and CNF-based environments (and Kubernetes) through Contiv-VPP support. The HCL solution based on the Intel FPGA PAC N3000 supports the following SRv6 endpoint behaviors, all of which enable SFC, L2VPN, and L3VPN: Static proxy (End.AS) Dynamic proxy (End.AD) Decapsulation and cross-connect (End.DX) Decapsulation and specific table lookup (End.DT) For more technical details, see the new Solution Brief titled “Accelerate SRv6 Processing.” (Click on the link to download the Solution Brief.) Notices and Disclaimers 1 Based on HCL testing on January 21, 2020. Test environment configuration: Intel® Xeon® Platinum 8180M processor (2.50 GHz, 56 cores), CentOS 7.6, kernel 3.10.957, Contiv-VPP v3.3.2.1 (VPP 19.08), Data Plane Development Kit (DPDK) v19.05, Ixia Network Tester, Intel FPGA PAC N3000, with up to four virtual machines (VMs) running L3 Forwarding; test topology: traffic generator connected back-to-back to the server host through optical cables. QSFP28 100 Gb port is broken out into 4 x 25 Gb; only two of them are used. For more information about testing, contact HCL. Performance results are based on testing as January 21, 2020, and may not reflect all publicly available security updates. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit intel.com/benchmarks. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at intel.com. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.F5 Networks BIG-IP VE for SmartNICs uses Intel® FPGA Programmable Acceleration Card N3000 to efficiently block incoming DDoS attacks in cloud environments while lowering TCO
Tom Atkins, a Product Marketing Manager at F5 Networks, has just published a blog that describes the company’s fully integrated BIG-IP Virtual Edition (VE) solution, which efficiently blocks incoming Distributed Denial of Service (DDoS) attacks in cloud environments using hardware acceleration to realize significant performance and total cost of ownership (TCO) gains. The solution consists of the F5 Networks BIG-IP AFM (Advanced Firewall Manager) Virtual Edition integrated with the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000 SmartNIC. In his blog, Atkins says that the combination of the F5 Networks BIG-IP AFM and the Intel FPGA PAC N3000 SmartNIC frees up CPU cycles for other functions and improves overall DDoS mitigation capacity. The result: The F5 Networks BIG-IP VE solution can handle DDoS attacks as much as 300X larger than software-only implementations while reducing TCO by approximately 47% by migrating CPU-intensive DDoS mitigation tasks including network threat intelligence, machine learning, packet-based analysis and white listing to the SmartNIC, which frees up high-value CPU cores to run revenue-generating cloud applications instead. For more information, read Atkins’ blog titled “Mitigate DDoS Attacks up to 300x Greater in Magnitude in Cloud Environments: Introducing BIG-IP VE for SmartNICs,” and then watch the associated 10-minute video from F5 Networks titled “Boosting BIG-IP VE Performance with Hardware Acceleration Technologies.” The video features F5 Networks Senior Strategic Architect Jason Rahm, who delves even further into the technical details of this topic. (Note: In the video, Rahm states that the F5 Networks BIG-IP AFM VE solution with the Intel® FPGA PAC N3000 SmartNIC delivers a 70X performance boost over a software-only implementation, but a footnote in the video’s description states that more recent testing has yielded performance improvements as large as 300X.) Also, please see the associated Solution Brief titled “High Capacity DDoS Protection in Cloud Environments with F5 BIG-IP VE for SmartNICs and Intel FPGA PAC N3000.” For more information about the Intel FPGA PAC N3000, click here. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices and Disclaimers Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. Intel and partners announce high-performance SmartNICs that deliver programmable network acceleration for cloud data centers and communications infrastructure
Intel has been a leader in Ethernet networking since the very beginnings of the IEEE 802 standard. The first Ethernet specification, Version 1.0, was published on September 30, 1980 – forty years ago. It was submitted as a candidate for the active IEEE project 802 local area network standardization effort. The original Ethernet specification document was called the “Blue Book” because of the light blue cover on the printed specification. Three company names appeared on that cover. One of those three names was Intel. Last week, just slightly more than forty years after the publication of that first Ethernet specification, Intel and its partners announced new, high-performance SmartNIC products that deliver programmable network acceleration for cloud data centers and communications infrastructure. The first such network acceleration product is the Inventec FPGA SmartNIC C5020X, which is based on the new Intel FPGA SmartNIC C5000X platform architecture designed to meet the needs of Cloud Service Providers. This new architecture boosts data center performance levels by off-loading switching, storage, and security functionality onto a single PCIe platform that combines both Intel FPGAs and Intel Xeon® processors. Customers can define and port custom networking functions to the Intel Stratix 10 FPGA. The familiarity of the Intel® Xeon-D processor integrated into the platform eases the porting effort. Inventec is one of the first ecosystem partners to leverage the Intel FPGA SmartNIC C5000X platform architecture. The second new SmartNIC is the Silicom FPGA SmartNIC N5010, a hardware-programmable 4x100G FPGA SmartNIC that combines an Intel Stratix 10 DX FPGA with an Intel® Ethernet 800 series adapter. The FPGA-based SmartNIC features enhanced packet buffering and traffic flow monitoring while extending connectivity to multiple 100G Ethernet ports. The Silicom FPGA SmartNIC N5010 delivers the performance and hardware programmability that Communications Service Providers need to accelerate 25G and 100G networks and Intel is partnering with Silicom to deliver this SmartNIC. The Intel FPGA SmartNIC C5000X platform and the new Silicom FPGA SmartNIC N5010 allow data center architects and network engineering teams at Telecom Equipment Manufacturers (TEMs), Virtual Network Function (VNF) vendors, system integrators, and telcos to supercharge their networks and to free up server CPU cycles for revenue-generating workloads. New SmartNIC products based on Intel® Stratix™ 10 FPGAs, Xeon-D processors, Intel Ethernet 800 series network adapters, and new platform architectures such as the Intel® FPGA SmartNIC C5000X platform help accelerate cloud data centers and communications infrastructure. Here are some quotes from Inventec, Silicom, other network ecosystem partners, and customers about these new SmartNIC products: “FPGAs have been the core of Azure’s SmartNIC infrastructure for multiple generations, providing us a high performance, flexible, and differentiated solution,” says Derek Chiou, a Partner Architect at Microsoft. “We are pleased to see Intel continue to lead the industry by launching the ground-breaking Intel FPGA SmartNIC Platform C5000X that will enable cloud service providers to integrate FPGA technology in their data centers to increase their efficiency, while providing flexibility to suit their needs.” continuing to lead the industry by launching the ground-breaking Smart NIC platform in Big Spring Canyon that can help ecosystem partners to enable cloud service providers to integrate FPGA technology in their data centers to increase their efficiency while providing flexibility to suit their own needs.” “Inventec is proud to have partnered with Intel to create a unique SmartNIC based upon the Intel® FPGA SmartNIC C5000X platform architecture,” says George Lin, General Manager of Business Unit VI, Inventec Enterprise Business Group (Inventec EBG). “We immediately realized that this platform would stand out as the SmartNIC for the future, offering customers the ability to customize while still delivering the outstanding performance, programmability, and portfolio of technology that only Intel can provide” “As a leading provider of connectivity solutions, it’s clear that SmartNICs can dramatically improve the performance and efficiency of 4G/5G edge deployments for Telco providers,” said Boris Beletsky, AVP, Emerging Technologies. "The Silicom FPGA SmartNIC N5010 is the first hardware programmable 200G FPGA accelerated SmartNIC that enables next generation IA-based servers to meet the performance and scaling needs of the 5G core network (UPF), access gateways (BNG, AGF), and security functions (Firewall, IPsec)." “Kaloom’s Programmable Networking Fabrics enable Telcos, Data Center Operators and CSPs to accelerate performance and monetization of millions of subscribers at the “Edge”, combining state of the art P4-enabled Intel Tofino switches, Stratix 10 FPGAs and Xeon processors in a fully virtualized manner (“slicing”)”, said Philippe Michelet, VP of Product Management. “By specifically leveraging Intel Stratix 10 FPGAs with integrated HBM2 memory running on the Silicom FPGA SmartNIC N5010, Kaloom can support several millions of subscribers as well as the statistics required by operators to correctly account for the data being processed by this new category of “Edge” data centers.” Click here for a fact sheet with more information about these announcements. Click here for more information about SmartNIC products from Intel. For more information about the Intel FPGA SmartNIC C5000X Platform, see the Solution Brief titled “Accelerate Your Data Center with Intel® FPGAs.” For more information about the Silicom FPGA SmartNIC PN5010, see the Solution Brief titled “SmartNICs with Intel® FPGAs Boost Performance for Converged Broadband Networks.” Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.The Next Platform discusses the latest Intel Networking Innovations including new Intel® SmartNICs based on Intel® FPGAs
Last month, Intel introduced several FPGA-based networking innovations, including the Intel® FPGA SmartNIC C5000X platform architecture – designed to meet the needs of Cloud Service Providers. Also announced: the Inventec FPGA SmartNIC C5020X, based on the Intel FPGA SmartNIC C5000X platform, and the Silicom FPGA SmartNIC N5010, a hardware-programmable 4x100G FPGA SmartNIC that combines an Intel® Stratix® 10 DX FPGA with an Intel® Ethernet 800 series adapter. (See “Intel and partners announce high-performance SmartNICs that deliver programmable network acceleration for cloud data centers and communications infrastructure.”) The Next Platform – an online publication dedicated to covering high-end computing at large enterprises, supercomputing centers, hyperscale data centers, and public clouds – discusses these and other network-related introductions from Intel in an article titled “Intel Networking: Not Just A Bag Of Parts,” written by the publication’s co-editor Timothy Prickett Morgan. The article features quotes from an interview with Hong Hou, Corporate Vice President and General Manager of the Connectivity Group at Intel, and it contains a large amount of analysis of the announced Intel networking innovations and offerings. Early in the article, Prickett Morgan had this to say: “Here is the reality: Companies will splurge on compute, by which we generally mean CPUs but increasingly GPUs and occasionally FPGAs, rather than memory or networking because they understand it better. Here is another fact that cannot be bargained with: The amount of data that is being shuttled around by networks in the datacenter is growing at 25 percent per year. But budgets cannot grow at that rate… “…it absolutely is desirable to have Intel be in the networking business and bring what it knows about the datacenter to bear.” Prickett Morgan then quotes from his interview with Hou: “For Intel, we want to provide intelligence and programmability in a flexible network that can handle the complexity of the emerging workloads. Our vision is to optimize all of these technology assets to provide enabling solutions for our customers – we are not just a supplier of a bag of parts.” Although the scope of these Intel offerings is quite wide and therefore hard to sum up in a few words, Prickett Morgan makes the effort. With respect to the FPGA-based introductions made last month, he writes: “What is interesting here is that the new Intel SmartNICs are not actually made by Intel, but by Inventec and Silicom, the former being an increasingly important ODM for hyperscalers and cloud builders and the latter being a network interface supplier for the past two decades. These devices sit on a spectrum along with the pure FPGA acceleration card, called the Programmable Acceleration Card, which we talked about when it first debuted with the [Intel® Arria® 10 FPGA] in October 2017 and when it was updated in September 2018 with the [Intel] Stratix 10 FPGA.” To read Timothy Prickett Morgan’s full article in The Next Platform, click here. For an associated editorial about these networking topics written by Hong Hou, see “Smart, Programmable Interconnects Unleash Compute Performance” in the Intel Newsroom. For more information about the October 15 Intel Networking event, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.New Video Demonstrates 116 Gbps PAM4 Transceiver Test Chip for Intel® Agilex™ I-Series FPGAs
A new Intel video shows the latest performance results for a high-speed, long-reach (LR) transceiver test chip operating at 116 Gbps with PAM4 modulation. The transceiver test chip, which is built with Intel 10 nm process technology, complies with the highest data rates of the CEI-112G-LR-PAM4 specification. The test chip’s 116 Gbps operation demonstrates the high-speed transceiver design’s added margin for existing 100/200/400 Gigabit Ethernet (GbE) standards and its ability to support emerging protocols and forward error-correction (FEC) standards. The video also shows the transceiver chip’s transmitter sending a 116 Gbps PRBS31 data pattern to a receiver on the same chip through interconnect and external cabling representing a total insertion loss of greater than 35 dB from BGA ball to BGA ball on the chip. In this test, the transceiver chip’s performance exceeds the CEI-112G-LR-PAM4 specification’s raw bit error ratio (BER) requirement by almost three orders of magnitude even at 116 Gbps, Here’s a screen shot showing the de-embedded PAM4 eye diagram of the transceiver chip’s transmitter operating at 116 Gbps measured with an oscilloscope. Measured PAM4 Eye Diagram with de-embedding of the I/O Transceiver Chip’s transmitter operating at 116 Gbps The high-speed, long-reach, digital ADC and DAC based transceiver architecture used for this chip along with a hardened 100/200/400 GbE protocol stack will be incorporated into Intel® Agilex™ I-Series FPGAs, which are optimized for high-speed, bandwidth-intensive networking in Cloud, Enterprise, and Edge applications. Here’s the 116 Gbps PAM4 Transceiver I/O Chip video: https://youtu.be/xR44OjF4moY For more information about this 116G LR PAM4 transceiver demonstration or to learn more about Intel Agilex FPGAs, please contact your local Intel salesperson. Notices and Disclaimers Transceiver TX compliance testing in accordance to Optical Interconnect Forum OIF CEI-112G-LR-PAM4 on Tuesday 3 rd March 2020 at 106.25 Gbps, 112 Gbps, and 116 Gbps. Equipment used: Keysight DCA-X Series Wide-Band Oscilloscope N1000A, 85 GHz bandwidth. Intel EV Transceiver Platform, Aim-TTi TGF4162 Dual Channel Arbitrary Function Generator, Agilent E3631A DC Triple Output Power Supply. Transceiver channel demonstration tested in accordance to OIF CEI-112G-LR-PAM4 specification on Tuesday 3 rd March 2020 at 116 Gbps data rate, ysung PRBS31 data pattern >35 dB insertion loss. Equipment used: Intel EV Transceiver Test Chip Platform, Intel QUISI Panel 1A (ISI Channel Board), Aim-TTi TGF4162 Dual Channel Arbitrary Function Generator, Agilent E3631A DC Triple Output Power Supply. 1 m Rosenberger RF cables (x2), 0.3 m Rosenberger RF cables (x2), 67 GHz DC blocks. Ardent Concepts Terminate-R Multicoax assembly plus 6 inch tails (x4). Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. The iAbra PathWorks toolkit brings embedded AI inference, real-time video recognition to the edge with Intel® Arria® 10 FPGAs, Intel® Xeon® Gold CPUs, and Intel® Atom® processors
It’s not always easy to get data to the cloud. Multi-stream computer vision applications, for example, are extremely data intensive and can overwhelm even 5G networks. A company named iAbra has created tools that build neural networks that run on FPGAs in real time, so that inference can be carried out at the edge in small, light, low-power embedded devices rather than in the cloud. Using what-you-see-is-what-you-get (WYSIWYG) tools, iAbra’s PathWorks toolkit creates neural networks that run on an Intel® Atom® x7-E3950 processor and an Intel® Arria® 10 FPGA in the embedded platform. The tools themselves run on an Intel® Xeon® Gold 6148 CPU to create the neural networks. From a live video stream, artificial intelligence (AI) can detect, for example, how many people are standing in a bus queue, which modes of transport people are using, and where there is flooding or road damage. In exceptional circumstances, AI can also alert emergency services if vehicles are driving against the traffic flow or if pedestrians have suddenly started running. Collecting reliable, real-time data from the streets and compressing it through AI inference makes it far easier to manage resources and to improve quality of life, productivity, and emergency response times in Smart Cities. To be effective, these vision applications must process a huge amount of data in real time. A single HD stream generates 800 to 900 megabits of streaming video data per second. That’s per camera. Although broadband 5G networks deliver more bandwidth and can greatly increase the device density within geographic regions, broadly and densely distributed armadas of video cameras still risk overwhelming these networks. The solution to this bandwidth constraint is to incorporate real-time AI inference at the network edge so that only the processed, essential information is sent to the cloud. That sort of processing requires an embedded AI device that can withstand the harsh environments and resource constraints found on the edge. iAbra has approached the problem of building AI inference into embedded devices by mimicking the human brain using FPGAs. Usually, image recognition solutions map problems to generic neural networks, such as ResNet. However, such networks are too big to fit into many FPGAs destined for embedded use. Instead, iAbra’s PathWorks toolkit constructs a new, unique neural network for each problem, which is tailored and highly optimized for the target FPGA architecture where it will run. In this case, the target architecture is an Intel Arria 10 FPGA. “We believe the Intel Arria 10 FPGA is the most efficient part for this application today, based on our assessment of the performance per watt,” said iAbra’s CTO Greg Compton. “The embedded platform also incorporates the latest generation Intel Atom processor, which provides a number of additional instructions for matrix processing over the previous generation. That makes it easier to do vector processing tasks. When we need to process the output from the neural network, we can do it faster with instructions that are better attuned to the application,” Compton explains. He adds: “A lot of our customers are not from the embedded world. By using Intel Atom processors, we enable them to work within the tried and tested Intel® architecture stack they know.” Similarly, said Compton: “We chose the Intel Xeon Gold 6148 processor for the network creation step as much for economics as performance.” iAbra developed this solution using OpenCL, a programming framework that makes FPGA programming more accessible by using a language similar to C, enabling code portability across different types of processing devices. iAbra also uses Intel® Quartus® Prime Software for FPGA design and development and the Intel® C++ Compiler to develop software. The company has incorporated Intel® Math Kernel Library (Intel® MKL), which provides optimized code for mathematical operations across a range of processing platforms. Compton continues: “With Intel MKL, Intel provides highly optimized shortcuts to a lot of low-level optimizations that really help our programmer productivity. OpenCL is an intermediate language that enables us to go from the high level WYSIWYG world to the low-level transistor bitmap world of FPGAs. We need shortcuts like these to reduce the problem domains, otherwise developing software like ours would be too big a problem for any one organization to tackle.” iAbra participates in the Intel FPGA Partner Program and Intel® AI Builders Program, which gives the company access to the Intel® AI DevCloud. “The Intel® AI DevCloud enables us to get cloud access to the very latest hardware, which may be difficult to get hold of, such as some highly specialized Intel® Stratix® 10 FPGA boards. It gives us a place where Intel customers can come and see our framework in a controlled environment, enabling them to try before they buy. It helped us with our outreach for a Smart Cities project recently. It’s been a huge help to have Intel’s support as we refine our solution, and develop our code using Intel’s frameworks and libraries. We’ve worked closely with the Intel engineers, including helping them to improve the OpenCL compiler by providing feedback as one of its advanced users,” Compton concludes. For more information about the iAbra Pathworks toolkit, please see the new Case Study titled “Bringing AI Inference to the Edge.” Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices & Disclaimers Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. 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