A Practical Look at the Shift from fixed ASSP to programmable FPGA
This post explores a practical shift from a fixed-function ASSP to a programmable FPGA platform in response to evolving system requirements. As bandwidth demands, protocol diversity, and feature complexity increased, limitations in a 400G optical transport ASSP and uncertainty in vendor roadmap made continued reliance difficult. The team transitioned to an FPGA-based approach, enabling customization of protocols and features while aligning the system more closely with real usage needs. The article also highlights benefits such as design reuse, reduced hardware variants, simplified inventory management, and greater control over long-term system evolution.Altera Extends Agilex®, MAX® 10, and Cyclone® V Lifecycles Through 2045 for Long-Life Systems
Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.
Pushing FPGA Fabric Performance Toward 1 GHz with Agilex® 7
Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.The FPGA Advantage for Secure 5G Infrastructure – A Dell Perspective
Dell’s Open RAN radio platforms use Altera Agilex® 7 SoC FPGAs to deliver secure, adaptable 5G infrastructure. The FPGA architecture enables hardware-rooted security and post-deployment updates, allowing radio units to evolve with new protocols and threats while maintaining trusted edge infrastructure.Altera and Pantherun Launch P4-based Next-Gen Configurable, Secure Networking at Embedded World 2026
At Embedded World 2026, Altera and Pantherun announced a collaboration to deliver flexible, secure, and high-performance networking solutions using FPGA technology. By combining Altera’s programmable platforms with Pantherun’s networking and security IP, the partnership enables scalable, future-ready architectures for industrial, telecom, and mission-critical systems.Teaching FPGAs and Microcontrollers to Share
Using FPGAs and MCUs Collaboratively FPGAs and microcontrollers can be used alternatively in some applications, but they can also be used cooperatively. FPGAs provide ultimate flexibility, but microcontrollers often include peripherals like USB or wireless interfaces that may be more convenient for communications and updates. Both devices require supporting circuitry such as power, reference clocks, and storage. Fortunately, these can often be shared when using FPGAs and microcontrollers together. This blog introduces an open-source tool that enables microcontrollers to load a programming file into a programmable device, and the practical application of this with the Raspberry Pi RP2350 MCU. An Open Standard for Loading Programmable Devices Loading programmable devices from embedded processors is a common task. The Jam Standard Test and Programming Language (STAPL) was originally developed by Altera engineers to address challenges in programming programmable logic devices (PLDs) in-system, such as proprietary file formats, vendor-specific algorithms, large file sizes, and long programming times. It provides a software-level standard for in-system programming (ISP), enabling flexibility and platform independence. Figure 1. In-system programming using the Jam File & Jam Player via an embedded processor. In August 1999, JAM/STAPL was adopted as JEDEC standard JESD-71, making it an industry-recognized solution for JTAG-based programming. The language introduced features like compact file formats, branching, and looping, which reduced programming time and file size—ideal for embedded systems. JAM/STAPL consists of two main components: Jam Composer: Generates Jam Files (.jam) containing programming algorithms and user data. Jam Player: Interprets these files and applies JTAG vectors for programming and testing devices. Over time, JAM/STAPL gained widespread support from PLD vendors, programming equipment makers, and test equipment manufacturers, becoming a cornerstone for in-field upgrades, prototyping, and production programming. Its evolution also included a byte-code format (.jbc) for even smaller files, making it suitable for resource-constrained embedded processors. Recently, Altera updated the license terms of the JAM and JBC players source code to MIT-0, to better clarify the usage rights. A Practical Example The CycloMod board is an example of an FPGA and microcontroller working cooperatively. The board combines a Raspberry Pi RP2350 MCU with a Cyclone® 10 LP FPGA in the SparkFun MicroMod form factor. In this board, the FPGA is connected to some of the edge connector I/O, while the RP2350 is used to provide a flexible USB interface. The boot ROM in the RP2350 is leveraged extensively for firmware and FPGA image updates. Figure 2. CycloMod Board At 22mm x 22mm (including the card-edge connector), the MicroMod form factor is quite compact. This necessitates sharing resources, as there is not much room for multiple oscillators or flash devices. The 12 MHz crystal oscillator in the RP2350 is easily shared by routing it to one of the GPIO clock outputs. Both the Cyclone 10 LP device and RP2350 rely on external storage, but this can also be shared. On this board, the flash is connected to the RP2350 to take advantage of the UF2 loading provided in the boot ROM, and the RP2350 loads the Cyclone FPGA. The Cyclone 10 LP device supports active configuration with an external SPI flash device, but it can also be configured/programmed passively through JTAG. Figure 3. CycloMod Block Diagram The STAPL byte code format (sometimes referred to as JBC) is compact enough to be used with microcontrollers like the RP2350. Altera provides source code for implementing the “players” to process these files in embedded systems. They offer players for the ASCII (JAM) and bytecode (JBC) versions of the files. Altera’s Quartus® software provides the option to generate JAM and JBC files. Since STAPL is a JEDEC standard, other FPGA vendors also support generating these files. Using the open-source code provided by Altera, the RP2350 is able to read a JBC file from flash and load the Cyclone 10 LP FPGA through the JTAG interface. A Python script is provided to convert the JBC files to the UF2 format, which the RP2350 uses for drag-n-drop programming. The script also adds a header with the file length and other details. Thanks to the ingenuity of the UF2 format created by Microsoft, this enables cross platform field updates with zero software to install. Results and Link to Source Porting Altera’s JBC player to the RP2350 eliminated the need for a second flash device and enabled user-friendly drag-n-drop FPGA updates. The port is available on GitHub if you want to use this in your system. https://github.com/steieio/pico-jbcSee the Next Wave of EW & Radar Technology
We’re gearing up for AOC 2025! From December 9–11, we’ll be at the Gaylord National Resort & Convention Center in National Harbor, Maryland for AOC2025—one of North America’s premier events dedicated to electronic warfare and radar. Visit us at booth #505 to discover the latest innovations in our Agilex™ 9 Direct RF and Agilex™ 5 product families. What to Expect at Altera’s Booth #505: 1. Wideband and Agility Demo using Agilex 9: Overview: Discover the power of frequency hopping with Altera’s Direct RF FPGA, enhancing system resilience and adaptability. Key Features: Demonstrates swift frequency changes and wideband monitoring. 2. Wideband Channelizer Demo using Agilex 9: Overview: Wideband Channelizer features polyphase filter and 65 phases FFT blocks with variable channel support. Key Features: Demonstrates sampling rate that supports 64 GSPS with 32GHz instantaneous bandwidth. 3. Direction of Arrival Demo using Agilex 5: Overview: Explore Direction of Arriaval estimation and signal detection using AI-based approach with deployment of neural networks. Key Features: Demonstrates neural networks implementation using DSP Builder Advanced Blockset (DSPBA), showcasing end-to-end operation running real time inference. 4. Altera COTS Partner Showcase: Come see our Agilex based COTS boards from partners including Annapolis Microsystems, CAES, Hitek, iWave Global, Mercury Systems, & Spectrum Controls. We are hosting customer meetings at the event, contact your local Altera salesperson to schedule a slot.
Addressing PQC and CRA with Crypto-Agile Security in Agilex™ Devices
A look at today’s evolving security requirements affecting the semiconductor industry, including post-quantum cryptography (PQC) and the Cyber Resilience Act (CRA), and how Altera’s latest capabilities in Agilex™ 3 and Agilex™ 5 FPGAs and SoCs are helping to enable future-proof security functions today.
Must-See Sessions & Demos at FPGA Conference Europe 2025!
Explore the top sessions, keynotes, and live demos from Altera and its Solution Acceleration Partners at FPGA Conference Europe 2025 in Munich. From AI, robotics, and DSP innovations to high-speed networking and quantum-safe security—discover what’s next in FPGA technology.
