Why does the Ethernet link fail to come up during the U‑Boot stage after reboot on the Agilex® 5 FPGA 013B Dev Kit GSRD HPS?
Description Due to an issue in the Quartus® Prime Pro Edition software version 25.3.1 GSRD release for the Agilex® 5 FPGA 013B Development Kit, the Ethernet link may fail to initialize during the U‑Boot stage after a reboot. When the dhcp command is executed, the Ethernet connection does not come up successfully and the following error message is displayed: Resolution This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software. Additional Information This issue occurs only when a reboot is performed after a successful power‑on. During the initial power‑on boot, the problem does not occur because the operating system uses a generic Ethernet driver. The issue arises because the Micrel PHY driver is not enabled by default in the U‑Boot configuration, causing the Ethernet link to fail during subsequent boot cycles.Why does the MIPI DSI‑2 FPGA IP design example fail when programming the FPGA on the Agilex® 3 FPGA and SoC C‑Series Development Kit?
Description Due to an issue in Quartus® Prime Pro Edition software version 26.1, users may encounter a failure when programming the FPGA with the .sof file generated by the MIPI DSI‑2 IP Design Example for the Agilex® 3 FPGA and SoC C‑Series Development Kit. This issue occurs because the design example generation script incorrectly maps the selected Agilex 3 development kit to an unintended target board. When configuring the FPGA using the Quartus Programmer, the following error may be reported: Error(18952): Error status: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0xXX Additionally, the FPGA part number shown in the generated example design may not match the FPGA device on the selected development kit. Resolution To work around this issue in Quartus® Prime Pro Edition software version 26.1, follow the steps below to generate the MIPI DSI‑2 IP Design Example for the correct Agilex® 3 FPGA device. 1. Open the Design Example Tab In the Quartus Prime Pro Edition software, open the MIPI DSI‑2 IP. Navigate to the Parameters window and ensure that the Design Example tab is selected at the top of the MIPI DSI‑2 IP GUI. 2. Select the Correct Target Board In the Target Development Kit section, open the Select Board drop‑down menu and choose the option that corresponds to your development kit, as shown in the table below: Development Kit Kit Part Number FPGA Part Number Target Board Option to Select Agilex® 3 FPGA and SoC C‑Series Development Kit DK‑A3W135BM16AEA A3CW135BM16AE6S Agilex® 3 FPGA C‑Series Development Kit Agilex® 3 FPGA C‑Series Development Kit DK‑A3Y135BM16AEA A3CY135BM16AE6S Agilex® 3 SoC C‑Series Development Kit Ensure that the selected target board option matches your development kit. 3. Generate the Design Example After selecting the correct target board option, click Generate Example Design and allow Quartus to complete the generation process. 4. Verify the FPGA Device Open the generated Quartus project and locate the device OPN in the Project Navigator. Verify that the device OPN (for example, A3CW135BM16AE6S) matches the FPGA part number listed for your development kit in the table above. If the device OPN matches, the design example has been generated correctly and can be programmed onto the FPGA. This problem affects only the target board selection mapping during design example generation for the Agilex® 3 FPGA and SoC C‑Series Development Kit. The MIPI DSI‑2 IP core and generated design examples are otherwise fully functional. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.
