Error: error deleting "<path>/0001_intel_pcie_ftile_mcdma_0_gen//pcie_ed_rp/pcie.qsf": permission denied
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier on a windows* 11 system, you may see the below error during generating example designs for F-tile PCIe Multichannel DMA IP for PCI Express IP. Error: error deleting "<user default temporary folder>/alt0446_17235589168751817424.dir/0001_intel_pcie_ftile_mcdma_0_gen//pcie_ed_rp/pcie.qsf": permission denied Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do we observe small increase in the duration of o_rx_pfc port assertion during the “PAUSE” state in the designs generated using F-Tile Ethernet Hard IP for F-Tile devices when cycles with incoming frames are padded?
Description An Ethernet design generated using F-Tile Ethernet hard IP in Quartus® Prime Pro Edition Software for F-Tile devices is showing small increase in the duration of o_rx_pfc port assertion for cycles with incoming padded frames. The slight increase in the duration of o_rx_pfc port assertion during the “PAUSE” state is due to the cycles carrying the padded data not contributing to the PAUSE time. For data rates ranging from 10G-200G, we observe an increase in the duration of 15ns for 10G and 2.5ns for 200G for each padded frame received during “PAUSE” state. 400G PFC implementation differs from other line rates so there won’t be any increase in duration of o_rx_pfc port assertion. Resolution There is no workaround and no plan to fix this problem.Why isn't the F-Tile Serial Lite IV Toolkit shown in the System Console window when using the Quartus® Prime Pro Edition software version 25.3 and 25.3.1 ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and 25.3.1, the F-Tile Serial Lite IV Toolkit is not shown in the System Console window. Resolution A patch is available to fix this problem for the Quartus Prime Pro Edition software versions 25.3.1. Download and install patch 1.11 below. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.
Generation of AOCL Report Failed with below error
Description Due to a problem in the FPGA Support Package for the oneAPI DCP++/C++ Compiler version 2024.2, you might see this error. Generation of AOCL Report Failed with the below error PLEASE submit a bug report to https://software.intel.com/en-us/support/priority-support and include the Stack dump: … aocl-opt 0x0000XXXXXXXXXXXX llvm::AccessGroupInfo::hasIndependentAGsOrSafelen(llvm::Loop*, llvm::Instruction*, llvm::Instruction*, int&) + 195 … or … aocl-opt: XXXXXXXX: llvm::Value::~Value(): Assertion `materialized_use_empty() && "Uses remain when a value is destroyed!"' failed. … Resolution To work around this problem, download and install the 2024.2.1 patch for the FPGA Support Package below. Determine where the 2024.2 Intel oneAPI DCP++/C++ Compiler is installed. The FPGA Support Package will be located inside of the compiler installation directory in the ‘oclfpga’ folder. For Linux, this will be ‘<install-dir>/intel/oneapi/compiler/2024.2/opt/oclfpga’, where <install-dir> is typically either ‘/opt’ or ‘~’. For Windows, this will usually be ‘C:\Program Files (x86)\Intel\oneAPI\compiler\2024.2\opt\oclfpga’. Rename the existing ‘oclfpga’ directory to something else, e.g., ‘oclfpga.bak’ or ‘oclfpga.prev’. Unpack the given archive, .tar.gz for Linux and .zip for Windows, to extract the ‘oclfpga’ folder and place it in ‘intel/oneapi/compiler/2024.2/opt’. (Optional) Remove the backup folder created in Step ‘2’ after testing. This problem is scheduled to be fixed in a future release of the FPGA Support Package for the oneAPI DCP++/C++ Compiler.Why does marginal degradation of 1.8V VIL I/O standard occur on Stratix® 10 FPGAs and Agilex™ FPGAs family SDM I/O pins after long-term operation?
Description On all Stratix® 10 FPGA and Agilex™ FPGA devices, when the board MSEL is set to JTAG but Quartus® Prime design software is configured to AS or AVST×8, and SDM I/O pins are left unconnected (NC), long-term operation may cause the 1.8V VIL on those SDM I/O pins to degrade below the datasheet specification of 0.5985V (0.35 × 1.71V). Refer to device datasheet under Single-Ended I/O Standards Specifications section for SDM IO I/O standard specification. The degradation can lead to configuration issues. Resolution Select AVST×16 as the configuration scheme in Quartus when using JTAG MSEL with all SDM I/O pins left unconnected. AVST×16 does not use any SDM I/O pins, preventing the degradation. Refer to Configuration User Guide for the steps to enable dual-purpose pins when setting AVSTx16 mode in Quartus. Starting in Quartus® Prime Pro edition software version 26.1, a note will be updated in the Configuration User Guide and the tooltips for the Configuration scheme category under Device and Pin Options in Quartus.Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1. Related Article NIOS V/g - peripherals under 2GB Peripheral Region | Altera Community - 350829Why do I see an Quartus® Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16-bit PMA interface?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you will see a Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16 bit PMA interface and placed in 200G Hard IP. The Quartus Logic Generation Error message might be similar to one of the followings: Error(22144) Error(22658) Error(21843) Resolution There is no plan to fix this problem. To work around this error, you can take one of the below two methods: Change the clocking mode from PMA clocking mode to System PLL clocking mode, or Change the F-Tile placement from 200G Hard IP to 400G Hard IP.Why does an error occur when upgrading Ethernet designs that use F‑Tile Ethernet Hard IP from Quartus® Prime Pro Edition version 22.4 or earlier to version 25.3.1?
Description Due to an issue in Quartus® Prime Pro Edition software version 22.4 and earlier, an error may be encountered when upgrading Ethernet designs created with F‑Tile Ethernet Hard IP to version 25.3.1. Error: ex_100G.eth_f_0: "Custom Ethernet line rate" (CUSTOM_RATE_GUI) 25.78125 is out of range: 10.3125-17.4 This problem is observed because the maximum supported line rate for the “Custom Ethernet line rate” was incorrectly changed to 17.4 Gbps. Resolution One workaround using the F‑Tile Ethernet Hard IP GUI is to open the .ip file, change the Ethernet mode to a different data rate, and then reconfigure it back to the original data rate. Alternatively, edit the .ip file directly by locating CUSTOM_RATE_GUI and changing its value from 25.78125 to 10.3125 Gbps. This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.What Agilex™ 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe* REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Agilex™ 7 FPGA Device Configuration via Protocol (CvP) Implementation User Guide Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*Why does GD55LB02GE QSPI flash fail in Linux* in FPGA SoC device?
Description If you use Linux* version between socfpga-6.0 and socfpga-6.12.43-lts with GD55LB02GE QSPI flash, you may fail to mount the file system in Linux if it’s stored in GD55LB02GE. This is caused by the gigadevice.c in these versions. Resolution This issue is fixed in socfpga-6.12.43-lts and afterwards. You can upgrade Linux source code to this version, or comment out the GD55LB02GE entry in gigadevice.c in old versions.