Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see this error message during the Support-Logic Generation stage when compiling a design on the Windows* Operating System. This error occurs when Windows* long path support is disabled. Windows* limits the combined length of a file name and its path to 260 characters. If the project path exceeds this limit, the Quartus® Software cannot access required IP or design files. Resolution To work around this problem, enable Windows* long path support by updating the registry: a) Open Registry Editor: Press Windows Key + R, type regedit, and press Enter. b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Find LongPathsEnabled. Double-click it and set "Value data" to 1. If the LongPathsEnabled doesn't exist, right-click, select New > DWORD (32-bit) Value, and name it LongPathsEnabled. d) Restart your computer. This error message will be enhanced in a future release of the Quartus ® Prime Pro Edition Software.Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_traversal_manager.cpp, Line: 2769
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 to 25.3.1, you might see this internal error at the Fitter Finalize stage when the design contains combinational loops. Static Timing Analysis analyzes timing graphs without loops. When a combinational loop is detected, Timing Analyzer replaces the loop with bypass edges whose delays represent the longest path through the loop. When new timing corners are added later in the finalize stage, the bypass edge delays may not be computed for all corners, causing an internal consistency check to fail and resulting in an internal error. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.Why is PTP enabled F-Tile Ethernet FPGA Hard IP design using Quartus® Prime Pro Edition showing an error when the PTP enabled F-Tile Ethernet FPGA Hard IP design is connected to System PLL1 clock or System PLL2 clock?
Description Due to a limitation in the Quartus® Prime Pro Edition Software, the F-Tile Ethernet FPGA Hard IP shows an error when PTP enabled design is connected to system PLL 1 clock. This problem is seen in designs that have multiple IPs and when the IP with PTP enabled is connected to System PLL 1 clock or System PLL2 clock. Resolution The workaround for this limitation is to connect PTP enabled F-Tile Ethernet FPGA Hard IP to System PLL0 clock only.Why do I see rx_ready not asserting, or incorrect TX data rates in Agilex® 7 F‑Tile or Agilex® 5/3 FPGA GTS device transceiver simulations using the Quartus® Prime Pro 25.3.1 or earlier software with Siemens QuestaSim® Altera Edition software?
Description Due to a bug in the Quartus® Prime Pro 25.3.1 and earlier software for Agilex® 7 F‑Tile or Agilex ® 5/3 FPGA GTS devices, you may see the rx_ready signal not asserting, or incorrect TX data rates when simulating with the Siemens QuestaSim* Altera® Edition software. Resolution To work around this problem, you can update your design to the Quartus Prime Pro software version 26.1 and create a script that sets the following environment variables and then calls the Quartus Prime Pro software generated msim_setup.tcl file. set QUARTUS_SIM_LIB_DIR <quartus_installation>/quartus/eda/sim_lib2 set DEVICES_SIM_LIB_DIR <quartus_installation>/devices/sim_lib2 set ENABLE_QE_LIBRARY_COMPILATION "true" source msim_setup.tcl This problem will be fixed in a future version of the Quartus Prime Pro software.Why does niosv-download return “Invalid reset option” when executing reset from debug module?
Description Due to a problem in the Ashling RiscFree IDE for Altera® software, the niosv-download returns “Invalid reset option” when executing reset from debug module for designs targeting Nios ® V processor. The affected versions are: Software version 25.2.1 (version dated 9 th May 2025, paired with Quartus® Prime Pro software version 25.1.1 and Quartus® Prime Standard software version 25.1) Software version 25.3.1 (version dated 1 st Aug 2025, paired with Quartus® Prime Pro software version 25.3.1) Software version 25.4.1 (version dated 31 st Oct 2025, paired with Quartus® Prime Pro software version 26.1) The problem is caused by Ashling GDBServer failing to execute software reset (swreset), and niosv-download is using Ashling GDBServer to communicate with the processor. Thus, this failure prompts the “Invalid reset option” message when executing “niosv-download –r". Resolution To work around this problem, use the argument “-o” to change from Ashling GDBserver to OpenOCD. $ niosv-download –r -o This problem is fixed beginning with the Ashling RiscFree IDE for Altera® Quartus® software version 26.1.1-C, which is paired with Quartus® Prime Pro software version 26.1.1. Related Articles NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10) | Altera Community - 352387Why does boundary scan fail or report length mismatches when including F-Tile FHT transceivers in the scan chain of Agilex® 7 FPGA devices when using Quartus® Prime Pro software version 26.1 or earlier?
Description Boundary scan of F-Tile FHT transceiver channels is not supported in Agilex® 7 FPGA devices when using the Quartus® Prime Pro software version 26.1 or earlier. Resolution To work around this problem, you can bypass the F-Tile FHT transceiver channels in your boundary scan chain. This problem will be fixed in a future version of the Quartus Prime Pro software.Why do setup and minimum pulse width timing violations occur in the LVDS SERDES IP Design Example?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1 and earlier, you may encounter setup and minimum pulse width timing violations in the LVDS SERDES IP Design Example. This issue is caused by an incorrect value of the vco_data_rate_ratio parameter used in the LVDS SERDES IP, which leads to improper timing constraints and resulting violations. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Resolution To work around this issue, follow the steps below: Step 1: In the auto-generated file intel_lvds_core10_ph2_hw_ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sv, Original: .vco_data_rate_ratio(0), Change to: .vco_data_rate_ratio(<correct_vco_data_rate_ratio>), Step 2: In the auto-generated file ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sdc, add this SDC constraint set ip_params(vco_data_rate_ratio) <correct_vco_data_rate_ratio> Step 3: Re-compile the design The correct vco_data_rate_ratio parameter value based on the LVDS SERDES IP data rate (Mbps) shown in table below: Use the appropriate vco_data_rate_ratio based on the LVDS SERDES IP data rate: data_rate >= 600 Mbps 1 600 Mbps > data_rate >= 300 Mbps 2 data_rate < 300 Mbps 4 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core: LVDS SERDES IPWhy does the Nios® V processor without data cache hang during a flash read operation using the Generic Serial Flash Interface (GSFI) IP HAL driver?
Description When performing a read operation on a flash device using the GSFI IP HAL driver, a Nios® V processor configured without a data cache may hang and stop functioning correctly due to an issue in the HAL driver. The HAL driver attempts to flush the data cache even when no data cache is present. This incorrect behavior places the processor into a non-deterministic state, which can cause the system to freeze. Resolution To work around this issue, update the following line in the intel_gsfi_read() function. Original: alt_dcache_flush_no_writeback((alt_u8*)qspi_flash_info->data_base + offset, length); Change to: #if ALT_CPU_DCACHE_SIZE > 0 alt_dcache_flush_no_writeback((alt_u8*)qspi_flash_info->data_base + offset, length); #endif This modification ensures that the data cache flush operation is performed only when a data cache is present. This issue will be fixed in a future Quartus® Prime Software release.Why does the read/write HAL API fail when the access length reaches the last byte of flash memory when using the Generic Serial Flash Interface (GSFI) IP HAL driver?
Description When performing a read or write operation on a flash memory device using the GSFI IP HAL read/write API, the API may incorrectly return an EINVAL error code. This issue occurs because the operation end address is miscalculated. As a result, the GSFI IP HAL API incorrectly determines that the operation end address exceeds the valid flash memory range and flags the access length as invalid. For example, when reading or writing the entire 1 GiB flash device, the operation reaches the last byte with an access length of 2147483648 bytes. In this case, the GSFI IP HAL API miscalculates the operation end address as 0x80000000, which exceeds the flash end address of 0x7FFFFFFF. Consequently, the access length is incorrectly treated as invalid, and a false EINVAL error code is returned. This issue does not occur when reading from or writing to other addresses that do not include the last byte of the flash memory. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Resolution To work around this issue, update the following line in the intel_gsfi_validate_read_write_arguments() Original: end_address = start_address + length; Change to: end_address = start_address + length - 1; This correction ensures the calculated end address does not exceed the valid flash memory range. This issue will be fixed in a future Quartus® Prime Design Software release.Why does an SDI hardware failure occur in single‑rate HD‑SDI parallel loopback without an external VCXO at 1280×720p24 across all FPGA device families?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1 and earlier, an SDI hardware failure may be observed when using the Single‑Rate HD‑SDI Parallel Loopback design without an external VCXO and selecting the 1280 × 720p24 video standard on all SDI‑supported FPGA device families. This issue does not affect multi‑rate or triple‑rate HD modes. Resolution This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. For users who must remain on Quartus® version 26.1 or earlier, use the following workaround: Regenerate the design using Quartus® Prime Pro Edition Software version 26.1.1 or later. In your target project, replace the entire pfd folder with the corresponding folder from the newly generated design. The updated PFD module can be found at: <Your_Design_Folder>/rtl/loopback/pfd