Qsys: EMIF IP Core: usr_reset associated Clock
Hello, I am a bit confused by the Usage of the emif_usr_reset_n signal of the Intel EMIF IP Core. I have added a EMIF IP Core to our Platform Designer project. Based on the Documentation (4.1.1.14. emif_usr_reset_n for DDR3) I would assume the usr_reset output to have an associated clock (emif_usr_clk) with a synchronous deassertion: However in Platform Designer this reset appears without any associated clock and I get reset adapters when assigning it to reset inputs which require synchronous deassertion. I tried to explicitly set the emif_usr_reset_n output associated clock and synchronous edge, by applying this setting: But then I end up with the following Warning and I can also confirm, that the corresponding emif.ip file does not have the expected associated clock setting. So my question is: Is the documentation (4.1.1.14. emif_usr_reset_n for DDR3) correct and is the emif_usr_reset_n output really synchronous deasserted? Why does Platform Designer does not recognize the correct clock association for this signal? How do I configure the IP in a correct way to avoid any unnecessary or unexpected automatically inserted reset adapter? best regards Fabian
