Are there any functional or security updates for the Quartus® Prime Standard Edition Software version 23.1.1?
Description The Quartus® Prime Standard Edition Software version 23.1.1 Patch 1.01std includes functional and security updates. Users should keep their software up-to-date and follow the technical recommendations to help improve security. If you need additional security updates, they will be provided in this article as they become available. Resolution A patch is available to include this update for the Quartus® Prime Standard Edition Software version 23.1.1 and the Quartus® Prime Lite Edition Software Version 23.1.1. Download and install Patch 1.01std below. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software and the Quartus® Prime Lite Edition Software.Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1. Related Article NIOS V/g - peripherals under 2GB Peripheral Region | Altera Community - 350829Errors: 'MODULAR_ADC_0_DUAL_ADC_MODE' undeclared here (not in a function)
Description Due to a problem with the Quartus® Prime Standard Edition Software version 21.1, when Modular ADC Core IP used in a Nios® II Gen 2 system, you might see the following errors when building the Nios® II software project: 'MODULAR_ADC_0_DUAL_ADC_MODE' undeclared here (not in a function) 'MODULAR_ADC_0_IRQ_INTERRUPT_CONTROLLER_ID' undeclared here (first use in this function) 'MODULAR_ADC_0_IRQ' undeclared here (first use in this function) 'MODULAR_ADC_0_NAME' undeclared here (not in a function) Resolution To work around this problem, the altera_modular_adc.h file located in \intelFPGA\21.1\ip\altera\altera_modular_adc\top\HAL\inc needs to be replaced with a new one. Download the driver.zip file to obtain the updated altera_modular_adc.h file. This problem is scheduled to be fixed in the Quartus® Prime Standard Edition Software version 22.1 and later versions.Why does the Nios® V processor fail to generate HDL with an add_fileset_file error message in Quartus® Prime Standard Edition from Windows OS?
Description Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This issue is present only on Windows OS. Example error message: Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr” This is because the Nios® V processor hw.tcl is calling add_fileset_file on an unsupported simulator. These unsupported simulators are referring to simulators that are not supported in Windows OS - Cadence Simulator and Synopsys VCS* and VCS MX. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 24.1, download and install the patches below. This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software. Additional Information For information on the simulators’ supported platforms, refer to the Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators.How to build Baremetal example on the Cyclone® V SoC FPGA with third-party ADRV9001 using the SoC FPGA Embedded Development Suite (SoC EDS) Standard Edition Software Version 2018.0?
Description Due to problems in the SoC FPGA Embedded Development Suite (SoC EDS) Standard Edition Software Version 2018.0, building the Baremetal example on the Cyclone® V SoC FPGA with third-party ADRV9001 failed. Resolution To workaround this problem, please find attached the document Baremetal-Example-Cyclone® V SoC FPGA with ADRV9001 using SoCEDS.pdf to follow the instructions to build and run the baremetal example on the Cyclone® V SoC FPGA with third-party ADRV9001 using the SoC FPGA Embedded Development Suite (SoC EDS) Standard Edition Software Version 2018.0.
Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why I can't open Early Power Estimators (EPE) tool in the latest version of Microsoft Excel?
Description There is a compatibility issue with the current EPE tools with the latest update from Microsoft* on the Excel version 2505 and later. The update from Microsoft causes the EPE tools to stop working. Resolution There is no plan to fix this. Users need to use the Excel version before version 2505 for the EPE tools to work. There is a workaround if the user needs to use the latest Excel version, please contact Altera support and quote this ID #15018720346How to mitigate the security vulnerability in the Nios® II Command Shell utility?
Description Due to a problem in the Quartus ® Prime Standard and Lite Edition Software version 19.1 through 24.1, the Nios® II Command Shell utility included in the Quartus ® Prime Software for Windows* is vulnerable to a Current Working Directory (CWD) planting attack. The Linux* versions are not affected. Resolution To work around this problem, replace the “Nios II Command Shell.bat” Windows Batch File located in the <drive>:\<edition>\<version number>\nios2eds\, with the attached file below. This problem is fixed beginning with the Quartus® Prime Standard and Lite Edition Software version 25.1.Why do I see timing violations in 1G/10G and 10GBASE-KR PHY FPGA IP?
Description Due to an issue in 1G/10G and 10GBASE-KR PHY FPGA IP, Quartus® Prime Standard Edition Design Software is unable to generate SDC file along with the IP files. Resolution As a workaround, download the file below. Check the following parameter values in the downloaded .sdc file and modify as per the design, if required: num_channels period_10g period_1g period_mgmt path_project
