We Hope to See You at Intel® FPGA Technology Day 2021
Intel® FPGA Technology Day (IFTD) is a free four-day event that will be hosted virtually across the globe in North America, China, Japan, EMEA, and Asia Pacific from December 6-9, 2021. The theme of IFTD 2021 is “Accelerating a Smart and Connected World.” This virtual event will showcase Intel® FPGAs, SmartNICs, and infrastructure processing units (IPUs) through webinars and demonstrations presented by Intel experts and partners. The sessions are designed to be of value for a wide range of audiences, including Technology Managers, Product Managers, Board Designers, and C-Level Executives. Attendees to this four-day event will learn how Intel’s solutions can solve the toughest design challenges and provide the flexibility to adapt to the needs of today’s rapidly evolving markets. A full schedule of Cloud, Networking, Embedded, and Product Technology sessions, each just 30 minutes long, will enable you to build the best agenda for your needs. Day 1 (December 6), TECHNOLOGY: FPGAs for a Dynamic Data Centric World: Advances in cloud infrastructure, networking, and computing at the edge are accelerating. Flexibility is key to keeping pace with this transforming world. Learn about innovations developed and launched in 2021 along with new Intel FPGA technologies that address key market transitions. Day 2 (December 7), CLOUD AND ENTERPRISE: Data Center Acceleration: The cloud is changing. Disaggregation improves data center performance and scalability but requires new tools to keep things optimized. Intel FPGA smart infrastructure enables smarter applications to make the internet go fast! Day 3 (December 8): EMBEDDED: Transformation at the Edge: As performance and latency continue to dictate compute’s migration to the edge, Intel FPGAs provide the workload consolidation and optimization required with software defined solutions enabled by a vast and growing partner ecosystem. Day 4 (December 9): NETWORKING: 5G – The Need for End-to-End Programmability: The evolution of 5G continues to push the performance-to-power envelop, requiring market leaders to adapt or be replaced. Solutions for 5G and beyond will require scalable and programmable portfolios to meet evolving standards and use cases. To explore the detailed program, see the featured speakers, and register for the North America event, Click Here. Register in other regions below: EMEA China Japan Asia Pacific
APS Networks launches three OpenBNG Broadband Network Gateways incorporating Intel® Xeon® D processors, Intel® Tofino™ Switch ASICs, and Intel® Stratix® 10 MX FPGAs
Open BNG is an initiative within the Open Optical & Packet Transport (OOPT) Project Group’s Disaggregated Open Routers (DOR) sub-group, which is all part of the global Telecom Infra Project (TIP) that’s working to accelerate the development and deployment of open, disaggregated, and standards-based connectivity technology. TIP announced the initial release of the OpenBNG Technical Requirements document for large scale fiber-to-the-home (FTTH) networks – developed collaboratively by Telefónica, Deutsche Telekom, BT, and Vodafone – last October. The document encompasses: Hardware and software requirements for an open and disaggregated Broadband Network Gateway (BNG) device that operators can deploy in current and future networks for the provision of fixed broadband services (OpenBNG) The role of software-defined networks (SDN) and the desired approach for fixed-mobile convergence The required hardware and proposed non-mutually exclusive software packages needed to support additional services or functionalities Reference regulatory requirements to deploy Open BNG in the networks of the operators participating in the development of this requirements document The OpenBNG specification allows operators a choice of different hardware platforms and types of network operating system (NOS) and control-plane applications, with goals of lowering the total cost of ownership and lowering the cost per broadband subscriber. APS Networks has just launched three BNG switches which aim to comply with TIP OpenBNG requirements. Operators can choose among the SC-1, SC-2, and SC-3 TIP standard configurations for leaf designs that best address their end-user demands and cover both full-functionality deployments and service-only BNG deployments. The APS Networks® announcement includes three BNG products: The Hyperion APS2172Q, supporting 64x1/10/25G BNG user ports & 8x100G spine ports (SC-1) The Jupiter APS6120Q with 16x100G BNG ports & 4x1/10/25G ports (SC-2) The Hyperion APS2140D with 32x1/10/25G BNG user ports & 8x100G spine ports (SC-3 leaf) The APS2172Q and APS6120Q each support as many as 32,000 broadband subscribers and the APS2140D supports as many as 20,000 broadband subscribers. The announced BNG switches incorporate Intel® Xeon® D processors, P4-programmable Intel® Tofino™ Ethernet switch ASICs, and Intel® Stratix® 10 MX FPGAs with High-Bandwidth Memory (HBM). All BNG switch models can be equipped with a Precision Time Protocol (PTP) IEEE 1588v2 compliant add-on module, which enables the switches to operate as PTP boundary clocks with end-to-end accuracies of better than 10nsec. Andy Heal, Chief Technology Officer for APS Networks, said “The APS Networks range of OpenBNG switches accelerate the possibilities for access edge solutions. Combining these low latency products of Intel Tofino P4-programmable switch ASICs and Intel Stratix 10 MX FPGAs, with world-class PTP capabilities and Intel Xeon D processors, APS Networks have designed and developed a unique range of network switches for the wireline broadband market.” For more information about these APS Networks OpenBNG switches, please contact APS Networks directly. Click here. For more information about Intel Xeon D processors, click here. For more information about the Intel Tofino Ethernet Switch ASIC, click here. For more information about Intel Stratix 10 FPGAs including the Intel Stratix 10 MX FPGAs, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, Xeon, Tofino, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel at MWC: Panel Discusses “How is the O-RU reference architecture driving 5G Radio Development?”
Telecom operators need to reduce development time and while implementing new solutions to increase the performance and reliability of 5G networks in a cost-effective manner. Operators have already implemented open systems in their network cores and virtualizing functions, and now they want to achieve the same benefits with RANs including Radio Units (RUs). The Open RU (O-RU) roadmap covers both traditional macro radios and Massive MIMO and addresses key challenges including overall design cost reduction and accelerated time-to-market without sacrificing system-level power and performance. A 30-minute panel discussion about O-RU developments titled “How is the O-RU reference architecture driving 5G Radio Development?” in the Intel® Network & Edge Panel Series discusses the key digital, analog, RF technology, and business considerations that will enable radio ODMs, CMs, and System Integrators to offer flexible and scalable end-to-end RAN solutions. Panel participants include: Tero Kola, VP, System Product Management, Mobile Networks Business Group, Nokia Francisco (Paco) Martin, Group Head of OPEN RAN, Vodafone Rajesh Srinivasa, SVP and GM, Radio Business Unit, Mavenir Mike Fitton, VP, Intel Programmable Solutions Network Business Division, Intel Corporation Nitin Sharma, GM, Wireless Communications, Analog Devices, Inc (ADI) Moderator: Guy Daniels, Director of Content, TelecomTV Interested? Click here to watch the panel discussion. Click here to see all of the panel discussions in the Intel® Network & Edge Panel Series. Click here to see all the Intel events at Mobile World Congress. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Designing High-Performance ATE, RF, or Communications Test Equipment? Here’s why you need Intel® Agilex™ FPGAs
It’s tough developing test equipment for leading-edge products because the test equipment must have all the functions and capabilities of the equipment being tested, and often just a bit more. This is a perfect place for using FPGAs, particularly the new, high-performance Intel® Agilex™ FPGAs and SoCs. If you are developing this type of test equipment, there’s an upcoming Webinar from Intel and Arrow titled Unleashing a New Generation of Test Equipment with Intel® Agilex™ FPGAs that might help you out. The Webinar will discuss real-world design and application insights for various types of ATE (Automatic test equipment) used in high-volume manufacturing test, RF test instrumentation, and communications testing. This Webinar takes place on March 22 and will be available on demand as well. Click here to register. For more information about Intel Agilex FPGAs and SoCs, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel’s new technology puts ADCs and DACs operating at 64 Gsamples/sec into packaged FPGAs
Intel has announced new technology that combines FPGA die with high-speed analog chiplets that incorporate both ADCs and DACs operating as fast as 64 Gsamples/sec. With analog sampling rates that fast, this technology represents a revolutionary step towards providing direct RF capability for radar, test & measurement, and wireless communications systems. This heterogeneous system-in-package technology leverages Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and the open standard Advanced Interface Bus (AIB) to seamlessly integrate the ADC/DAC chiplet with the FPGA die. Beamforming systems used in radar and other mission critical applications are currently designed with 32 or more antenna elements sharing a single analog converter. This new architecture significantly increases algorithm complexity and requires substantially more digital signal processing (DSP), memory, and logic FPGA resources. As a result, these systems are now transitioning to wider bandwidth, all-digital designs, where each antenna element connects directly to an ADC and DAC. This all-digital architecture reduces the amount of data transmitted through a system and speeds the transmission of actionable information to enable more rapid decision making by placing required computing resources closer to the sensor. Intel’s state-of-the-art heterogeneous packaging technology can connect chiplets from different processing nodes, including the ADC/DAC chiplet, to the FPGA fabric. This packaging technology connects chiplets using thousands of wires, each operating at 1 Tbps, using EMIB interconnect technology and the AIB physical layer protocol. Combining the high-speed converters with the FPGA in one packaged device eliminates the need for SERDES or JESD204 package-to-package interconnects and significantly reduces power consumption. The first Intel offering to employ this technology will feature an analog data converter with input sample rates up to 64 Gsamples/sec. This offering will combine high-performance ADCs and DACs with a high-density, high-performance FPGA fabric and other dedicated transceiver chiplets in one package. For more information, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.SmartNICs based on Intel® FPGAs Boost Converged Broadband Network Performance
To meet consumer demands, telco providers that offer both wireless and wireline access to customers rely on dual, complex fixed and mobile infrastructures that must constantly be upgraded and maintained at great cost. Consequently, telco Internet providers continuously explore new ways to reduce costs and create new revenue streams. Many operators, for example, are eyeing 5G fixed-mobile convergence (FMC) to lower costs and add new agile services. FMC also helps telco providers to meet the customer needs. Both consumer and business customers are looking for multi-access connectivity and a seamless service experience. Innovations such as software-defined networking (SDN) and network function virtualization (NFV), are key to enabling the network transformation at the telco’s edge. These innovations support new capabilities including the User Plane Function (UPF), the Access Gateway Function (AGF), and Broadband Network Gateway (BNG). The combination of these new capabilities enables higher throughput and lower latency for traffic between the telco central office (CO) and broadband customers, both wireless and wireline, through a newly shared infrastructure. Finding the right hardware on which to host these new virtual network functions (VNFs) at the network edge is a big challenge because telco COs must upgrade infrastructure while meeting physical space, power, and cooling constraints. The hardware solution also must be sufficiently cost-effective to support the additional, ever present goals for reducing capital expenditures (CapEx) and operating expenses (OpEx). Finally, the solution needs to scale to handle tens of thousands―or even hundreds of thousands―of subscriber connections. SmartNICs built with Intel® FPGAs provide solutions to these challenges while still offering the advantages of a commercial off-the-shelf (COTS) solution. One such SmartNIC, just announced by Silicom, is the Silicom FPGA SmartNIC N5010. This SmartNIC is a high-performance, programmable PCIe server adapter that combines an Intel Stratix 10 DX FPGA – which integrates high performance, high-bandwidth memory (HBM) – and an Intel® Ethernet 800 series adapter. Use these SmartNICs to accelerate the UPF, AGF, and BNG functions and to realize many performance benefits including high-throughput packet processing, smart and effective packet load balancing to CPU cores, and Hierarchical Quality of Service (HQoS). These capabilities are crucial to support high bandwidth and low latency in converged access networks. A new Solution Brief from Intel titled “SmartNICs with Intel® FPGAs Boost Performance for Converged Broadband Networks” discusses these topics in more detail. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel and partners announce high-performance SmartNICs that deliver programmable network acceleration for cloud data centers and communications infrastructure
Intel has been a leader in Ethernet networking since the very beginnings of the IEEE 802 standard. The first Ethernet specification, Version 1.0, was published on September 30, 1980 – forty years ago. It was submitted as a candidate for the active IEEE project 802 local area network standardization effort. The original Ethernet specification document was called the “Blue Book” because of the light blue cover on the printed specification. Three company names appeared on that cover. One of those three names was Intel. Last week, just slightly more than forty years after the publication of that first Ethernet specification, Intel and its partners announced new, high-performance SmartNIC products that deliver programmable network acceleration for cloud data centers and communications infrastructure. The first such network acceleration product is the Inventec FPGA SmartNIC C5020X, which is based on the new Intel FPGA SmartNIC C5000X platform architecture designed to meet the needs of Cloud Service Providers. This new architecture boosts data center performance levels by off-loading switching, storage, and security functionality onto a single PCIe platform that combines both Intel FPGAs and Intel Xeon® processors. Customers can define and port custom networking functions to the Intel Stratix 10 FPGA. The familiarity of the Intel® Xeon-D processor integrated into the platform eases the porting effort. Inventec is one of the first ecosystem partners to leverage the Intel FPGA SmartNIC C5000X platform architecture. The second new SmartNIC is the Silicom FPGA SmartNIC N5010, a hardware-programmable 4x100G FPGA SmartNIC that combines an Intel Stratix 10 DX FPGA with an Intel® Ethernet 800 series adapter. The FPGA-based SmartNIC features enhanced packet buffering and traffic flow monitoring while extending connectivity to multiple 100G Ethernet ports. The Silicom FPGA SmartNIC N5010 delivers the performance and hardware programmability that Communications Service Providers need to accelerate 25G and 100G networks and Intel is partnering with Silicom to deliver this SmartNIC. The Intel FPGA SmartNIC C5000X platform and the new Silicom FPGA SmartNIC N5010 allow data center architects and network engineering teams at Telecom Equipment Manufacturers (TEMs), Virtual Network Function (VNF) vendors, system integrators, and telcos to supercharge their networks and to free up server CPU cycles for revenue-generating workloads. New SmartNIC products based on Intel® Stratix™ 10 FPGAs, Xeon-D processors, Intel Ethernet 800 series network adapters, and new platform architectures such as the Intel® FPGA SmartNIC C5000X platform help accelerate cloud data centers and communications infrastructure. Here are some quotes from Inventec, Silicom, other network ecosystem partners, and customers about these new SmartNIC products: “FPGAs have been the core of Azure’s SmartNIC infrastructure for multiple generations, providing us a high performance, flexible, and differentiated solution,” says Derek Chiou, a Partner Architect at Microsoft. “We are pleased to see Intel continue to lead the industry by launching the ground-breaking Intel FPGA SmartNIC Platform C5000X that will enable cloud service providers to integrate FPGA technology in their data centers to increase their efficiency, while providing flexibility to suit their needs.” continuing to lead the industry by launching the ground-breaking Smart NIC platform in Big Spring Canyon that can help ecosystem partners to enable cloud service providers to integrate FPGA technology in their data centers to increase their efficiency while providing flexibility to suit their own needs.” “Inventec is proud to have partnered with Intel to create a unique SmartNIC based upon the Intel® FPGA SmartNIC C5000X platform architecture,” says George Lin, General Manager of Business Unit VI, Inventec Enterprise Business Group (Inventec EBG). “We immediately realized that this platform would stand out as the SmartNIC for the future, offering customers the ability to customize while still delivering the outstanding performance, programmability, and portfolio of technology that only Intel can provide” “As a leading provider of connectivity solutions, it’s clear that SmartNICs can dramatically improve the performance and efficiency of 4G/5G edge deployments for Telco providers,” said Boris Beletsky, AVP, Emerging Technologies. "The Silicom FPGA SmartNIC N5010 is the first hardware programmable 200G FPGA accelerated SmartNIC that enables next generation IA-based servers to meet the performance and scaling needs of the 5G core network (UPF), access gateways (BNG, AGF), and security functions (Firewall, IPsec)." “Kaloom’s Programmable Networking Fabrics enable Telcos, Data Center Operators and CSPs to accelerate performance and monetization of millions of subscribers at the “Edge”, combining state of the art P4-enabled Intel Tofino switches, Stratix 10 FPGAs and Xeon processors in a fully virtualized manner (“slicing”)”, said Philippe Michelet, VP of Product Management. “By specifically leveraging Intel Stratix 10 FPGAs with integrated HBM2 memory running on the Silicom FPGA SmartNIC N5010, Kaloom can support several millions of subscribers as well as the statistics required by operators to correctly account for the data being processed by this new category of “Edge” data centers.” Click here for a fact sheet with more information about these announcements. Click here for more information about SmartNIC products from Intel. For more information about the Intel FPGA SmartNIC C5000X Platform, see the Solution Brief titled “Accelerate Your Data Center with Intel® FPGAs.” For more information about the Silicom FPGA SmartNIC PN5010, see the Solution Brief titled “SmartNICs with Intel® FPGAs Boost Performance for Converged Broadband Networks.” Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Nokia AirFrame Edge Server based on 2nd Gen Intel® Xeon® Scalable CPUs and the Intel® FPGA PAC N3000 suits edge and far-edge cloud RAN, MEC, and 5G deployments
Nokia AirFrame open edge servers feature an ultra-small footprint so they fit well in many locations including existing base station facilities and far-edge sites. These compact servers are provisioned with a real-time, OPNFV compatible, OpenStack distribution that provides both low latency and high throughput for cloud RAN and other applications. The software runs atop integrated 2 nd Generation Intel® Xeon® Scalable CPUs and the optional Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000, which enhance the server’s capabilities with respect to artificial intelligence (AI) and machine learning (ML) workloads. An optional Fronthaul Gateway module provides 5G/4G/CPRI connectivity to existing legacy radios and contains an L2/L3 switch and an Intel® Stratix® 10 FPGA, which provides high-performance L1 processing. The servers are available in OCP-accepted 2RU or 3RU chassis with as many as five server sled slots and dual redundant AC or DC power supplies. Nokia offers both 1U and 2U server sleds based on 2 nd Generation Intel Xeon Scalable processors with connectivity through front server slots for high accessibility. A new 4-minute Nokia video details the features and benefits of the Nokia AirFrame open edge server for use in a variety of deployments including Cloud RAN, Multi-access Edge Computing (MEC), and 5G. For more technical details about the Nokia AirFrame open edge server, please contact Nokia directly. Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.ServeTheHome.com publishes in-depth, hands-on review of the Supermicro SYS-1019P-FHN2T SuperServer with an Intel® FPGA Programmable Acceleration Card N3000
ServeTheHome.com (STH), a Web site that bills itself as “the IT professional's guide to servers, storage, networking, and high-end workstation hardware,” recently published a hands-on review of the Supermicro SuperServer SYS-1019P-FHN2T – a 1U edge server based on the Intel® Xeon® Scalable processor with an integrated Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000 – which can be used to accelerate 5G and network functions virtualization (NFV) workloads for telecommunications equipment manufacturers (TEMs), virtual network functions (VNF) vendors, system integrators, and telcos. The article, written by STH’s Editor in Chief Patrick Kennedy, is titled “Supermicro SYS-1019P-FHN2T with Intel PAC N3000 Hands-on” and includes a 12-minute embedded video featuring Kennedy, who visited the Supermicro offices in person to review the Supermicro SYS-1019P-FHN2T SuperServer with a hands-on perspective. In discussing the Intel FPGA PAC N3000, Kennedy writes: “The PAC N3000 was designed for systems like the Supermicro SYS-1019P-FHN2T as it is designed for 5G service provider edge deployments. Instead of this FPGA card having to be part of a larger custom solution, Intel can offer the card in a PCIe form factor, housed in the SYS-1019P-FHN2T making it flexible.” Kennedy has been running STH since 2009. This article and the embedded video pack a lot of Kennedy’s insights regarding edge servers, their design, and their myriad uses. The article concludes with Kennedy writing: “The global 5G mobile build-out is a huge opportunity. Companies like Supermicro and Intel have systems like the Supermicro SYS-1019P-FHN2T with the Intel FPGA PAC N3000 precisely to address the unique requirements of the 5G edge deployments.” Click on the link above to read the full article on the STH site. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices & Disclaimers Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. Check with your system manufacturer or retailer or learn more at www.intel.com. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results may not reflect all publicly available security updates. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.The iAbra PathWorks toolkit brings embedded AI inference, real-time video recognition to the edge with Intel® Arria® 10 FPGAs, Intel® Xeon® Gold CPUs, and Intel® Atom® processors
It’s not always easy to get data to the cloud. Multi-stream computer vision applications, for example, are extremely data intensive and can overwhelm even 5G networks. A company named iAbra has created tools that build neural networks that run on FPGAs in real time, so that inference can be carried out at the edge in small, light, low-power embedded devices rather than in the cloud. Using what-you-see-is-what-you-get (WYSIWYG) tools, iAbra’s PathWorks toolkit creates neural networks that run on an Intel® Atom® x7-E3950 processor and an Intel® Arria® 10 FPGA in the embedded platform. The tools themselves run on an Intel® Xeon® Gold 6148 CPU to create the neural networks. From a live video stream, artificial intelligence (AI) can detect, for example, how many people are standing in a bus queue, which modes of transport people are using, and where there is flooding or road damage. In exceptional circumstances, AI can also alert emergency services if vehicles are driving against the traffic flow or if pedestrians have suddenly started running. Collecting reliable, real-time data from the streets and compressing it through AI inference makes it far easier to manage resources and to improve quality of life, productivity, and emergency response times in Smart Cities. To be effective, these vision applications must process a huge amount of data in real time. A single HD stream generates 800 to 900 megabits of streaming video data per second. That’s per camera. Although broadband 5G networks deliver more bandwidth and can greatly increase the device density within geographic regions, broadly and densely distributed armadas of video cameras still risk overwhelming these networks. The solution to this bandwidth constraint is to incorporate real-time AI inference at the network edge so that only the processed, essential information is sent to the cloud. That sort of processing requires an embedded AI device that can withstand the harsh environments and resource constraints found on the edge. iAbra has approached the problem of building AI inference into embedded devices by mimicking the human brain using FPGAs. Usually, image recognition solutions map problems to generic neural networks, such as ResNet. However, such networks are too big to fit into many FPGAs destined for embedded use. Instead, iAbra’s PathWorks toolkit constructs a new, unique neural network for each problem, which is tailored and highly optimized for the target FPGA architecture where it will run. In this case, the target architecture is an Intel Arria 10 FPGA. “We believe the Intel Arria 10 FPGA is the most efficient part for this application today, based on our assessment of the performance per watt,” said iAbra’s CTO Greg Compton. “The embedded platform also incorporates the latest generation Intel Atom processor, which provides a number of additional instructions for matrix processing over the previous generation. That makes it easier to do vector processing tasks. When we need to process the output from the neural network, we can do it faster with instructions that are better attuned to the application,” Compton explains. He adds: “A lot of our customers are not from the embedded world. By using Intel Atom processors, we enable them to work within the tried and tested Intel® architecture stack they know.” Similarly, said Compton: “We chose the Intel Xeon Gold 6148 processor for the network creation step as much for economics as performance.” iAbra developed this solution using OpenCL, a programming framework that makes FPGA programming more accessible by using a language similar to C, enabling code portability across different types of processing devices. iAbra also uses Intel® Quartus® Prime Software for FPGA design and development and the Intel® C++ Compiler to develop software. The company has incorporated Intel® Math Kernel Library (Intel® MKL), which provides optimized code for mathematical operations across a range of processing platforms. Compton continues: “With Intel MKL, Intel provides highly optimized shortcuts to a lot of low-level optimizations that really help our programmer productivity. OpenCL is an intermediate language that enables us to go from the high level WYSIWYG world to the low-level transistor bitmap world of FPGAs. We need shortcuts like these to reduce the problem domains, otherwise developing software like ours would be too big a problem for any one organization to tackle.” iAbra participates in the Intel FPGA Partner Program and Intel® AI Builders Program, which gives the company access to the Intel® AI DevCloud. “The Intel® AI DevCloud enables us to get cloud access to the very latest hardware, which may be difficult to get hold of, such as some highly specialized Intel® Stratix® 10 FPGA boards. It gives us a place where Intel customers can come and see our framework in a controlled environment, enabling them to try before they buy. It helped us with our outreach for a Smart Cities project recently. It’s been a huge help to have Intel’s support as we refine our solution, and develop our code using Intel’s frameworks and libraries. We’ve worked closely with the Intel engineers, including helping them to improve the OpenCL compiler by providing feedback as one of its advanced users,” Compton concludes. For more information about the iAbra Pathworks toolkit, please see the new Case Study titled “Bringing AI Inference to the Edge.” Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices & Disclaimers Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.