Can the new Intel® eASIC™ devices help you reach your 4G and 5G equipment design goals?
By Ronnie Vasishsta, VP and GM, Intel Corporation There is a lot of discussion in the industry today surrounding 5G telecommunications and networking. I even see television commercials about 5G popping up more and more. What's lost in all the excitement about 5G is that the 4G and 4G Advanced Pro standards are still in the deployment phase – and the equipment is still evolving. Many current telecom and networking use cases can be met with these existing 4G solutions and they serve as a bridge to 5G. As a result, vendors are now developing flexible equipment that can implement 4G standards now, with an eye towards reconfiguring them to 5G later. What 5G adds is not just new technologies but also new business models. Yes, 5G offers enhanced speed on mobile broadband, but the 5G technologies also add some new use cases. For example, some of these new use cases take advantage of new 5G capabilities such as massive machine-to-machine communications that are being used to facilitate smart factories, autonomous driving, enhanced video analytics, more accurate location tracking and a plethora of others. So 5G brings new capabilities, new use cases, and enhanced speed to the networking and telecom markets. Because these generational transitions from 4G to 5G are happening so quickly, and because 4G itself is evolving with new technologies such as massive MIMO, millimeter wave, beamforming, and carrier aggregation, it’s very hard for 4G and 5G equipment vendors to work with a fixed set of hardware solutions. Equipment vendors’ customers are looking for adaptable, configurable solutions to meet the changing needs of their customers. These solutions often must not only be software-configurable; they must take advantage of configurable hardware – meaning reconfigurable silicon – to meet some of the new technology latency, performance, power and cost requirements of these increasingly advanced networks. Intel is ideally situated to aid equipment vendors and their customers with this transformation as various 4G deployments and 5G standards are released. Intel software- and hardware-programmable products allow customers to accommodate the constant need for network reconfiguration while still maintaining performance, power, and cost targets. For these 4G and 5G applications, Intel® Xeon® CPUs, Intel® FPGAs, Intel® eASIC™ devices, and Intel® ASICs are very complementary products. Intel FPGAs can very efficiently implement certain functions within specific telecom and networking standards while offering benefits in terms of performance and cost. These FPGAs give equipment makers the option to quickly accelerate network functionality to an Intel FPGA sitting immediately adjacent to the Intel Xeon CPU. This migration option is especially attractive when Intel Xeon CPU cycles can better be used for revenue-generating tasks rather than for lower-level tasks. More efficiencies can be gained by moving the offloaded functions from the Intel FPGA to an Intel eASIC structured ASIC as designs mature and as feature sets solidify. Intel eASIC devices allow reuse of IP from FPGA-based designs and can cut power consumption by as much as 50% at the same clock frequency relative to the same designs implemented in FPGAs while also lowering unit costs. In addition, developing a design using an Intel eASIC device requires only half of the time needed to develop an ASIC with similar capabilities. The broad offering of Intel Xeon CPUs, Intel FPGAs, Intel eASIC devices, and Intel ASICs really gives equipment vendors the ability to carefully manage their product life cycles as their designs pass through various product phases from prototypes, to early production, to mature production volumes. Intel has introduced the next generation of Intel eASIC devices, code-named Diamond Mesa. These new Intel eASIC Diamond Mesa devices will consume less power and will be faster than the existing Intel eASIC N3XS products. In addition, these new Intel eASIC Diamond Mesa devices incorporate a multicore, embedded, hard processor subsystem, which means that these devices can implement control functions as well as well as many DSP and networking functions on a single device. The hard processor subsystem incorporated into the Intel eASIC Diamond Mesa devices allows the identical software to operate on both the new Intel® Agilex™ SoCs and the Intel eASIC Diamond Mesa devices. Structured ASICs like Diamond Mesa balance the configurability and fast time-to-market of FPGAs with the power-efficient, purpose-built performance of custom ASICs, and are a key piece of Intel’s 5G solution portfolio. Software and hardware portability across devices is a hallmark of Intel FPGAs and Intel eASIC devices. Significant know-how developed over many years permits Intel to migrate FPGA-based designs into an Intel eASIC structured ASIC quickly and easily while reusing much of the IP. In addition, Intel is moving some of the migration work to automated tools, which makes the process even faster and easier. However, your design need not target an Intel FPGA for easy migration to an Intel eASIC device. Intel has developed techniques to migrate designs from any vendor’s FPGA into Intel eASIC structured ASICs. Some customers that are familiar with Intel eASIC structured ASIC devices already target these devices directly for specific end products without ever targeting an FPGA. (Or, perhaps the FPGA is used for prototyping, in preparation for a conversion to an Intel eASIC device.) In such cases, a tool flow called eTools, which combines several in-house hardware development tools created by Intel, eases migration and helps customers implement their designs directly in the Intel eASIC fabric. It’s also possible to migrate from an eASIC device to a full-mask-set ASIC should the project’s power or unit-cost goals require it. Networking and telecom equipment OEMs and companies building out 4G and 5G infrastructure networks should review the full line of Intel semiconductor and IP products in the light of their cost and power targets to determine how to best take advantage of the full breadth of the unique Intel device offerings. These products help equipment vendors put multiple products with the right bill of materials and the right price point into the market quickly for those with limited R&D budgets. Legal Notices and Disclaimers: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com. 2X Higher Performance or 50% Lower Power based on circuit simulations for the same function performed September 2019. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configuration details and may not reflect all publicly available security updates. No product or component can be absolutely secure. Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice Revision #20110804 Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel’s new technology puts ADCs and DACs operating at 64 Gsamples/sec into packaged FPGAs
Intel has announced new technology that combines FPGA die with high-speed analog chiplets that incorporate both ADCs and DACs operating as fast as 64 Gsamples/sec. With analog sampling rates that fast, this technology represents a revolutionary step towards providing direct RF capability for radar, test & measurement, and wireless communications systems. This heterogeneous system-in-package technology leverages Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and the open standard Advanced Interface Bus (AIB) to seamlessly integrate the ADC/DAC chiplet with the FPGA die. Beamforming systems used in radar and other mission critical applications are currently designed with 32 or more antenna elements sharing a single analog converter. This new architecture significantly increases algorithm complexity and requires substantially more digital signal processing (DSP), memory, and logic FPGA resources. As a result, these systems are now transitioning to wider bandwidth, all-digital designs, where each antenna element connects directly to an ADC and DAC. This all-digital architecture reduces the amount of data transmitted through a system and speeds the transmission of actionable information to enable more rapid decision making by placing required computing resources closer to the sensor. Intel’s state-of-the-art heterogeneous packaging technology can connect chiplets from different processing nodes, including the ADC/DAC chiplet, to the FPGA fabric. This packaging technology connects chiplets using thousands of wires, each operating at 1 Tbps, using EMIB interconnect technology and the AIB physical layer protocol. Combining the high-speed converters with the FPGA in one packaged device eliminates the need for SERDES or JESD204 package-to-package interconnects and significantly reduces power consumption. The first Intel offering to employ this technology will feature an analog data converter with input sample rates up to 64 Gsamples/sec. This offering will combine high-performance ADCs and DACs with a high-density, high-performance FPGA fabric and other dedicated transceiver chiplets in one package. For more information, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
We Hope to See You at Intel® FPGA Technology Day 2021
Intel® FPGA Technology Day (IFTD) is a free four-day event that will be hosted virtually across the globe in North America, China, Japan, EMEA, and Asia Pacific from December 6-9, 2021. The theme of IFTD 2021 is “Accelerating a Smart and Connected World.” This virtual event will showcase Intel® FPGAs, SmartNICs, and infrastructure processing units (IPUs) through webinars and demonstrations presented by Intel experts and partners. The sessions are designed to be of value for a wide range of audiences, including Technology Managers, Product Managers, Board Designers, and C-Level Executives. Attendees to this four-day event will learn how Intel’s solutions can solve the toughest design challenges and provide the flexibility to adapt to the needs of today’s rapidly evolving markets. A full schedule of Cloud, Networking, Embedded, and Product Technology sessions, each just 30 minutes long, will enable you to build the best agenda for your needs. Day 1 (December 6), TECHNOLOGY: FPGAs for a Dynamic Data Centric World: Advances in cloud infrastructure, networking, and computing at the edge are accelerating. Flexibility is key to keeping pace with this transforming world. Learn about innovations developed and launched in 2021 along with new Intel FPGA technologies that address key market transitions. Day 2 (December 7), CLOUD AND ENTERPRISE: Data Center Acceleration: The cloud is changing. Disaggregation improves data center performance and scalability but requires new tools to keep things optimized. Intel FPGA smart infrastructure enables smarter applications to make the internet go fast! Day 3 (December 8): EMBEDDED: Transformation at the Edge: As performance and latency continue to dictate compute’s migration to the edge, Intel FPGAs provide the workload consolidation and optimization required with software defined solutions enabled by a vast and growing partner ecosystem. Day 4 (December 9): NETWORKING: 5G – The Need for End-to-End Programmability: The evolution of 5G continues to push the performance-to-power envelop, requiring market leaders to adapt or be replaced. Solutions for 5G and beyond will require scalable and programmable portfolios to meet evolving standards and use cases. To explore the detailed program, see the featured speakers, and register for the North America event, Click Here. Register in other regions below: EMEA China Japan Asia PacificIntel at MWC: Panel Discusses “How is the O-RU reference architecture driving 5G Radio Development?”
Telecom operators need to reduce development time and while implementing new solutions to increase the performance and reliability of 5G networks in a cost-effective manner. Operators have already implemented open systems in their network cores and virtualizing functions, and now they want to achieve the same benefits with RANs including Radio Units (RUs). The Open RU (O-RU) roadmap covers both traditional macro radios and Massive MIMO and addresses key challenges including overall design cost reduction and accelerated time-to-market without sacrificing system-level power and performance. A 30-minute panel discussion about O-RU developments titled “How is the O-RU reference architecture driving 5G Radio Development?” in the Intel® Network & Edge Panel Series discusses the key digital, analog, RF technology, and business considerations that will enable radio ODMs, CMs, and System Integrators to offer flexible and scalable end-to-end RAN solutions. Panel participants include: Tero Kola, VP, System Product Management, Mobile Networks Business Group, Nokia Francisco (Paco) Martin, Group Head of OPEN RAN, Vodafone Rajesh Srinivasa, SVP and GM, Radio Business Unit, Mavenir Mike Fitton, VP, Intel Programmable Solutions Network Business Division, Intel Corporation Nitin Sharma, GM, Wireless Communications, Analog Devices, Inc (ADI) Moderator: Guy Daniels, Director of Content, TelecomTV Interested? Click here to watch the panel discussion. Click here to see all of the panel discussions in the Intel® Network & Edge Panel Series. Click here to see all the Intel events at Mobile World Congress. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Nokia AirFrame Edge Server based on 2nd Gen Intel® Xeon® Scalable CPUs and the Intel® FPGA PAC N3000 suits edge and far-edge cloud RAN, MEC, and 5G deployments
Nokia AirFrame open edge servers feature an ultra-small footprint so they fit well in many locations including existing base station facilities and far-edge sites. These compact servers are provisioned with a real-time, OPNFV compatible, OpenStack distribution that provides both low latency and high throughput for cloud RAN and other applications. The software runs atop integrated 2 nd Generation Intel® Xeon® Scalable CPUs and the optional Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000, which enhance the server’s capabilities with respect to artificial intelligence (AI) and machine learning (ML) workloads. An optional Fronthaul Gateway module provides 5G/4G/CPRI connectivity to existing legacy radios and contains an L2/L3 switch and an Intel® Stratix® 10 FPGA, which provides high-performance L1 processing. The servers are available in OCP-accepted 2RU or 3RU chassis with as many as five server sled slots and dual redundant AC or DC power supplies. Nokia offers both 1U and 2U server sleds based on 2 nd Generation Intel Xeon Scalable processors with connectivity through front server slots for high accessibility. A new 4-minute Nokia video details the features and benefits of the Nokia AirFrame open edge server for use in a variety of deployments including Cloud RAN, Multi-access Edge Computing (MEC), and 5G. For more technical details about the Nokia AirFrame open edge server, please contact Nokia directly. Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Open vSwitch for NFVi based on Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 achieves first-packet learning rate of 500K rules/sec, near-wireline performance
As the numbers of subscribers, competitors, and technology advances grow, communications service providers (CoSPs) need to differentiate their products and services while keeping improved power efficiency and the need to control total cost of ownership (TCO) as ever-present goals. Intel and HCL have addressed these challenges with a joint solution that combines Intel® hardware and HCL software. HCL has created a solution using the Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 that can dramatically increase network functions virtualization infrastructure (NFVi) routing and switching performance while preserving flexibility. The resulting solution, the Open vSwitch (OvS), is a production quality, multilayer virtual switch that can implement software-defined networking (SDN), which is crucial to creating a closed-loop, fully automated NFVi solution. The OvS can either forward packets through a kernel-based datapath or by using the Linux Data Plane Development Kit (DPDK). Aggressive software optimization offloads NFVi forwarding tasks to the Intel FPGA PAC N3000, yielding the following preliminary results 1 : For more details, see the new Solution Brief titled “Increase NFVi Performance and Flexibility.” (Click on the link to download the Solution Brief.) Notices and Disclaimers 1 Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at intc.com. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Hardware Acceleration and Segment Routing over IPv6 (SRv6) help CoSPs Optimize and Simplify their Networks
Communications service providers (CoSPs) are seeking ways to differentiate themselves and to enhance their customers’ experiences in the fast-evolving telecommunication (telco) market—all while keeping costs under control. Exponential traffic growth and constant pressure to add more services and subscribers can tax legacy infrastructure, forcing CoSPs to constantly optimize and simplify their networks. Many CoSPs have deployed network functions virtualization (NFV) in an effort to optimize their networks. However, an influx of new subscribers and growing data loads consume a growing number of CPU cycles simply to route traffic, which leaves fewer compute resources to run actual containerized network functions (CNFs) and virtualized network functions (VNFs) that CoSPs want to support. The end result: suboptimal performance and the need for more hosts. To help overcome these challenges, CoSPs are turning to technologies such as hardware acceleration and segment routing over IPv6 (SRv6). SRv6 helps address the requirements of NFV and software-defined networking (SDN) architecture. It provides a unified solution for networking programmability, service function chaining (SFC), protocol simplification, traffic engineering, and mobile and fixed network convergence. An SRv6 solution from Intel and HCL overcomes network bottlenecks and achieves up to 3x savings in processor cores by offloading low-level SRv6 processing to the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000. The card is reprogrammable and delivers the flexibility that CoSPs need to support new networking workloads. HCL has built an optimized architecture that enhances network throughput and predictability while reducing latency by taking advantage of the plugin-based framework of vector packet processing (VPP) and by offloading CPU-intensive operations to the Intel FPGA PAC N3000. The solution frees up CPU cores by offloading CPU-intensive segment-routing functions to the Intel FPGA PAC N3000, which means that four CPU cores in the hardware-assisted solution can deliver comparable performance to 12 cores running a software-based SRv6. That’s a 3x savings in CPU cores as shown in the graphic below. 1 Freed CPU cores and cycles can be dedicated to vital CNF workloads running on that networking infrastructure instead of networking infrastructure. The solution’s small footprint can help reduce power and cooling costs. It is available for both VNF-based environments through VPP support and CNF-based environments (and Kubernetes) through Contiv-VPP support. The HCL solution based on the Intel FPGA PAC N3000 supports the following SRv6 endpoint behaviors, all of which enable SFC, L2VPN, and L3VPN: Static proxy (End.AS) Dynamic proxy (End.AD) Decapsulation and cross-connect (End.DX) Decapsulation and specific table lookup (End.DT) For more technical details, see the new Solution Brief titled “Accelerate SRv6 Processing.” (Click on the link to download the Solution Brief.) Notices and Disclaimers 1 Based on HCL testing on January 21, 2020. Test environment configuration: Intel® Xeon® Platinum 8180M processor (2.50 GHz, 56 cores), CentOS 7.6, kernel 3.10.957, Contiv-VPP v3.3.2.1 (VPP 19.08), Data Plane Development Kit (DPDK) v19.05, Ixia Network Tester, Intel FPGA PAC N3000, with up to four virtual machines (VMs) running L3 Forwarding; test topology: traffic generator connected back-to-back to the server host through optical cables. QSFP28 100 Gb port is broken out into 4 x 25 Gb; only two of them are used. For more information about testing, contact HCL. Performance results are based on testing as January 21, 2020, and may not reflect all publicly available security updates. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit intel.com/benchmarks. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at intel.com. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel and partners announce high-performance SmartNICs that deliver programmable network acceleration for cloud data centers and communications infrastructure
Intel has been a leader in Ethernet networking since the very beginnings of the IEEE 802 standard. The first Ethernet specification, Version 1.0, was published on September 30, 1980 – forty years ago. It was submitted as a candidate for the active IEEE project 802 local area network standardization effort. The original Ethernet specification document was called the “Blue Book” because of the light blue cover on the printed specification. Three company names appeared on that cover. One of those three names was Intel. Last week, just slightly more than forty years after the publication of that first Ethernet specification, Intel and its partners announced new, high-performance SmartNIC products that deliver programmable network acceleration for cloud data centers and communications infrastructure. The first such network acceleration product is the Inventec FPGA SmartNIC C5020X, which is based on the new Intel FPGA SmartNIC C5000X platform architecture designed to meet the needs of Cloud Service Providers. This new architecture boosts data center performance levels by off-loading switching, storage, and security functionality onto a single PCIe platform that combines both Intel FPGAs and Intel Xeon® processors. Customers can define and port custom networking functions to the Intel Stratix 10 FPGA. The familiarity of the Intel® Xeon-D processor integrated into the platform eases the porting effort. Inventec is one of the first ecosystem partners to leverage the Intel FPGA SmartNIC C5000X platform architecture. The second new SmartNIC is the Silicom FPGA SmartNIC N5010, a hardware-programmable 4x100G FPGA SmartNIC that combines an Intel Stratix 10 DX FPGA with an Intel® Ethernet 800 series adapter. The FPGA-based SmartNIC features enhanced packet buffering and traffic flow monitoring while extending connectivity to multiple 100G Ethernet ports. The Silicom FPGA SmartNIC N5010 delivers the performance and hardware programmability that Communications Service Providers need to accelerate 25G and 100G networks and Intel is partnering with Silicom to deliver this SmartNIC. The Intel FPGA SmartNIC C5000X platform and the new Silicom FPGA SmartNIC N5010 allow data center architects and network engineering teams at Telecom Equipment Manufacturers (TEMs), Virtual Network Function (VNF) vendors, system integrators, and telcos to supercharge their networks and to free up server CPU cycles for revenue-generating workloads. New SmartNIC products based on Intel® Stratix™ 10 FPGAs, Xeon-D processors, Intel Ethernet 800 series network adapters, and new platform architectures such as the Intel® FPGA SmartNIC C5000X platform help accelerate cloud data centers and communications infrastructure. Here are some quotes from Inventec, Silicom, other network ecosystem partners, and customers about these new SmartNIC products: “FPGAs have been the core of Azure’s SmartNIC infrastructure for multiple generations, providing us a high performance, flexible, and differentiated solution,” says Derek Chiou, a Partner Architect at Microsoft. “We are pleased to see Intel continue to lead the industry by launching the ground-breaking Intel FPGA SmartNIC Platform C5000X that will enable cloud service providers to integrate FPGA technology in their data centers to increase their efficiency, while providing flexibility to suit their needs.” continuing to lead the industry by launching the ground-breaking Smart NIC platform in Big Spring Canyon that can help ecosystem partners to enable cloud service providers to integrate FPGA technology in their data centers to increase their efficiency while providing flexibility to suit their own needs.” “Inventec is proud to have partnered with Intel to create a unique SmartNIC based upon the Intel® FPGA SmartNIC C5000X platform architecture,” says George Lin, General Manager of Business Unit VI, Inventec Enterprise Business Group (Inventec EBG). “We immediately realized that this platform would stand out as the SmartNIC for the future, offering customers the ability to customize while still delivering the outstanding performance, programmability, and portfolio of technology that only Intel can provide” “As a leading provider of connectivity solutions, it’s clear that SmartNICs can dramatically improve the performance and efficiency of 4G/5G edge deployments for Telco providers,” said Boris Beletsky, AVP, Emerging Technologies. "The Silicom FPGA SmartNIC N5010 is the first hardware programmable 200G FPGA accelerated SmartNIC that enables next generation IA-based servers to meet the performance and scaling needs of the 5G core network (UPF), access gateways (BNG, AGF), and security functions (Firewall, IPsec)." “Kaloom’s Programmable Networking Fabrics enable Telcos, Data Center Operators and CSPs to accelerate performance and monetization of millions of subscribers at the “Edge”, combining state of the art P4-enabled Intel Tofino switches, Stratix 10 FPGAs and Xeon processors in a fully virtualized manner (“slicing”)”, said Philippe Michelet, VP of Product Management. “By specifically leveraging Intel Stratix 10 FPGAs with integrated HBM2 memory running on the Silicom FPGA SmartNIC N5010, Kaloom can support several millions of subscribers as well as the statistics required by operators to correctly account for the data being processed by this new category of “Edge” data centers.” Click here for a fact sheet with more information about these announcements. Click here for more information about SmartNIC products from Intel. For more information about the Intel FPGA SmartNIC C5000X Platform, see the Solution Brief titled “Accelerate Your Data Center with Intel® FPGAs.” For more information about the Silicom FPGA SmartNIC PN5010, see the Solution Brief titled “SmartNICs with Intel® FPGAs Boost Performance for Converged Broadband Networks.” Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.SmartNICs based on Intel® FPGAs Boost Converged Broadband Network Performance
To meet consumer demands, telco providers that offer both wireless and wireline access to customers rely on dual, complex fixed and mobile infrastructures that must constantly be upgraded and maintained at great cost. Consequently, telco Internet providers continuously explore new ways to reduce costs and create new revenue streams. Many operators, for example, are eyeing 5G fixed-mobile convergence (FMC) to lower costs and add new agile services. FMC also helps telco providers to meet the customer needs. Both consumer and business customers are looking for multi-access connectivity and a seamless service experience. Innovations such as software-defined networking (SDN) and network function virtualization (NFV), are key to enabling the network transformation at the telco’s edge. These innovations support new capabilities including the User Plane Function (UPF), the Access Gateway Function (AGF), and Broadband Network Gateway (BNG). The combination of these new capabilities enables higher throughput and lower latency for traffic between the telco central office (CO) and broadband customers, both wireless and wireline, through a newly shared infrastructure. Finding the right hardware on which to host these new virtual network functions (VNFs) at the network edge is a big challenge because telco COs must upgrade infrastructure while meeting physical space, power, and cooling constraints. The hardware solution also must be sufficiently cost-effective to support the additional, ever present goals for reducing capital expenditures (CapEx) and operating expenses (OpEx). Finally, the solution needs to scale to handle tens of thousands―or even hundreds of thousands―of subscriber connections. SmartNICs built with Intel® FPGAs provide solutions to these challenges while still offering the advantages of a commercial off-the-shelf (COTS) solution. One such SmartNIC, just announced by Silicom, is the Silicom FPGA SmartNIC N5010. This SmartNIC is a high-performance, programmable PCIe server adapter that combines an Intel Stratix 10 DX FPGA – which integrates high performance, high-bandwidth memory (HBM) – and an Intel® Ethernet 800 series adapter. Use these SmartNICs to accelerate the UPF, AGF, and BNG functions and to realize many performance benefits including high-throughput packet processing, smart and effective packet load balancing to CPU cores, and Hierarchical Quality of Service (HQoS). These capabilities are crucial to support high bandwidth and low latency in converged access networks. A new Solution Brief from Intel titled “SmartNICs with Intel® FPGAs Boost Performance for Converged Broadband Networks” discusses these topics in more detail. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Arrow Electronics™ develops four complete RF reference platforms based on the Intel® Arria® 10 SoC FPGA and Analog Devices high-speed RF transceivers, ADCs, and DACs
The JESD204B serial interface has become the interface standard of choice for high-speed analog-to-digital and digital-to-analog converters (ADCs and DACs). Intel® FPGAs and Intel® SOC FPGAs are well suited to interface to these converters using this interface and Arrow Electronics™ has developed four JESD204B reference solutions using high-speed analog RF transceivers and converter modules based on Analog Devices RF transceivers, ADCs, and DACs. These solutions employ third party carrier board platforms from Critical Link and iWave supporting production-ready Systems on Modules (SOMs) based on Intel® Arria® 10 SOC FPGAs. The hardware for each of these platforms includes: An Intel Arria 10 SoC FPGA SOM A carrier card with an FMC HPC connector An Analog Devices FMC converter board Example reference designs for the platforms include: JESD204B HDL code for the Intel Arria 10 SoC FPGA Bootable Linux operating system image Custom IIO Linux device drivers Support for IIO Oscilloscope, an Analog Devices developed Linux user space application Each reference platform also includes a unique Quick Start Guide and complete source code for an example design. All documentation is now freely available on GitHub. The four Arrow Electronics reference platforms are: The ADRV9371 Platform: The ADRV9371 Platform is a complete development platform for applications that require high-performance radios capable of operating over a wideband frequency range. This platform is based on the Analog Devices AD9371 dual RF transceiver, which has a tunable range of 300 MHz to 6000 MHz. The ADRV9371 FMC converter evaluation board connects to the Intel Arria 10 SoC FPGA using the JESD204B serial interface over an FMC connector at lane rates as high as 6.144 Gbps. The ADRV9375 Platform: Similar to the ADRV9371 Platform, the ADRV9375 Platform connects an Intel Arria 10 SoC FPGA to an ADRV9375 evaluation board through an FMC connector using a JESD204B serial interface operating at lane rates as high as 6.144 Gbps. The Analog Devices ADRV9375 evaluation board is based on the Analog Devices AD9375 dual RF transceiver, which is similar to the Analog Devices AD9371 dual RF transceiver, but the AD9375 dual RF transceiver adds an on-chip digital pre-distortion (DPD) algorithm block. The AD-FMCDAQ2 Platform: This platform connects an Intel Arria® 10 SoC FPGA to an AD-FMCDAQ2 evaluation board over an FMC connector using the JESD204B serial interface operating at lane rates as high as 6.144 Gbps. The AD-FMCDAQ2 evaluation board incorporates an Analog Devices AD9144 high-speed DAC and an Analog Devices AD9680 high-speed ADC. The ADRV9371, ADRV9375, and AD-FMCDAQ2 reference platforms are ideal for developing a wide range of RF applications including: 3G/4G micro and macro base stations 3G/4G multicarrier picocells FDD and TDD antenna systems Microwave NLOS backhaul systems Test and measurement applications Software defined radios (SDR) The ADRV9009 Platform: This platform connects an Intel Arria® 10 SoC FPGA to an Analog Devices ADRV9009 evaluation board over an FMC connector using the JESD204B serial interface operating at lane rates as high as 12.288 Gbps. The Analog Devices’ ADRV9009 is a wide bandwidth, high performance RF integrated transceiver with dual transmitters; dual receivers; and a dual-input, shared-observation receiver. This platform is ideal for developing a wide range of RF applications including: 3G/4G/5G TDD Macro Cell Base Stations TDD Active Antenna Systems Massive MIMO Phased Array Radar Electronic Warfare Military Communications Portable Test Equipment Loaner kits are available from Arrow Electronics for customers to evaluate these solutions. Please contact your local Arrow rep for more information. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
