Will the receiver side of a transceiver channel be available during ATX PLL calibration of Stratix V GX/GT and Arria V GZ devices?

Description

During initial ATX PLL calibration immediately after configuration of Stratix® V GX/GT and Arria® V GZ devices, the receiver will not be available. Subsequent ATX PLL calibration processes initiated by the user will not affect the receiver data path.

........ATX PLL..RX.........

Updated 3 months ago

Version 3.0

arria® v fpgas and socs

stratix® v fpgas

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Knowledge Base Article

Will the receiver side of a transceiver channel be available during ATX PLL calibration of Stratix V GX/GT and Arria V GZ devices?

Description

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