Why might I see hold time, timing violations when enabling fast pipeline registers in the Intel® Stratix® 10 TX device E-Tile Native PHY IP when using Intel Quartus® Prime software version 18.1?

Description

Due to a bug in the Intel Quartus Prime 18.1 software, you might I see hold time, timing violations when enabling fast pipeline registers in the Intel Stratix 10 TX device E-Tile Native PHY IP when using Intel Quartus Prime software version 18.1.

Resolution

To work around this problem and meet timing, you can disable fast pipeline registers in the Intel Stratix 10 TX device E-Tile Native PHY IP or perform a seed sweep.

This problem will be fixed in a future version of the Intel Quartus Prime software.