Why is the functionality of my VHDL-2008 conditional signal assignment incorrect?

Description

Due to a problem in the Quartus® Prime Pro Edition Software, you might see that the following code is not implemented correctly.

example_process : process (clk)
begin
    if rising_edge(clk) then
        signal_1 <= input_a;
        signal_1 <= input_b when select_signal;
    end if;
end process example_process;

This should create a registered mux but instead creates a register with input_b connected to D input and select_signal used as the enable.

This code is only valid in VHDL-2008.

Resolution

To work around this problem, use this code instead.

example_process : process (clk)
begin
    if rising_edge(clk) then
        signal_1 <= input_b when select_signal else input_a;
    end if;
end process example_process;