Knowledge Base Article

Why does my simple dual-port memory not function correctly in RTL simulation?

Description

Due to a problem in the Quartus® II software version 11.1 and later, the altsyncram simulation model incorrectly delays the output data by one extra clock cycle when reading from a simple dual-port memory implemented using MLAB resources. This issue occurs when the read-during-write option is set to Old data.

Resolution

A patch is available to fix this problem in the Quartus II software version 11.1 SP2. Download and install patch 2.32 from the appropriate link below:

This problem is fixed beginning with the Quartus II software version 12.0 SP1.

Updated 3 months ago
Version 2.0
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