Why does my Cadence NCSIM Arria® V FPGA PCIe simulation fail complete getting stuck in L0 and timeout?

Description

Due to an issue when simulating the Arria® V FPGA Hard IP for PCI Express using Cadence NCSim  in the Quartus® II software version 13.0SP1 the simulation models must be updated.

Resolution

The updated files can be found at NewArriaVModelFiles.zip and replace the existing files in  the following location:

<your Quartus version>\quartus\eda\sim_lib\cadence

This problem has been fixed starting in the Quartus® II software version 14.0.