Why does my altera_syncram IP function incorrectly in simulation?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, you may see incorrect functionality for  altera_syncram IPs when using the Synopsys* VCS*/VCS MX* simulator version Q-2020.03-SP2. Incorrect behavior includes but is not limited to incorrect data output and incorrect data being written into the memory.

Resolution

To work around this problem, perform RTL simulation with Synopsys* VCS*/VCS MX version P-2019.06 or earlier.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.