Why do I see incorrect port values during simulation of custom Platform Designer components when using the TERMINATION port property?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software v22.1, when a SystemVerilog HDL interface input port is terminated then the HDL code generated by Platform Designer has no declaration of the signals being assigned the termination values.

For example, when the following settings are applied:

add_sv_interface bus mem_ifc
set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus

set_port_property address_in SV_INTERFACE_SIGNAL bus

set_port_property address_in TERMINATION true
set_port_property address_in TERMINATION_VALUE 0xFF

 

Platform Designer will generate the  incorrect HDL code missing the first line:

     logic [7:0] address_in;

my_ip my_ip_0 (
    .bus (my_ip_0_bus)  // interface,  width = 1, mem_ifc.bus
);

assign my_ip_0_bus.address_in = address_in;

assign address_in = 10'b0011111111;

Resolution

A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 22.1. Download and install Patch 0.12 from the appropriate link below

Download patch 0.12 for Windows (.exe)

Download patch 0.12 for Linux (.run)

Download the Readme for patch 0.12 (.txt)

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.2.