Why do I see hold time violations in the Intel® MAX® 10 FPGA On-Chip Flash in the Intel® Quartus® Prime Software version 15.1?

Description

Due to a problem in the timing model in the Intel® Quartus® Prime Software version 15.1, you might see timing violations in the Intel MAX® 10 FPGA On-Chip Flash on the following register:

*altera_onchip_flash_block:altera_onchip_flash_block|drdout[0]

Note that this register is both the source and destination for the hold violation.

Resolution

This violation is false and can be ignored. This problem has been fixed in the Intel Quartus Prime Software v15.1.1