Why do I see functional problems when simulating the 20.3 version of the Avalon® Streaming Single Clock FIFO Intel® FPGA IP in the Synopsys VCS simulator?

Description

Due to the way that the Synopsys VCS simulator handles mixed language (VHDL and verilog) simulation, you may encounter functional errors when simulating the v20.3 and later version of the Avalon® Streaming Single Clock FIFO Intel® FPGA IP core.

Resolution

To work around this problem, add the -deraceclockdata VCS argument during simulation.