Timing Violation in Arria V Devices Using Soft Logic Transceiver with Speed Grade 6

Description

Arria V device with speed grade 6 may have timing violation when using soft logic transceiver. When timing violation occurs, rxdata is not locked or will have a long locking time, causing unnatural behavior in the serial digital interface (SDI) core.

This issue affects all Arria V devices in 12.1.

Resolution

Turning on some of the parameters in the physical synthesis optimizations tab or switching the fitter effort to standard fit in fitter settings might resolve the issue.

This issue will be fixed in 12.1sp1.