Some Low Latency 40-100GbE IP Core Register Addresses Do Not Match User Guide

Description

Several registers in the Low Latency 40-100GbE IP core are available at actual addresses that do not match the addresses documented in the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide.

Actual location of TX statistics module TXSTAT_NAME_2 register is 0x84E

Actual location of RX statistics module RXSTAT_NAME_2 register is 0x94E

Actual location of PTP module TX_PTP_CLK_PERIOD register is 0xA01

Actual location of PTP module TX_PTP_TOD register is 0xA02 to 0xA04

Actual location of PTP module TX_PTP_STATUS is 0xA05

Actual location of PTP module RX_TP_CLK_PERIOD is 0xB01

Resolution

To work around this issue, use the actual addresses listed in this erratum to access these registers. Some of these actual locations are documented to hold scratch registers or IP core variation identifier strings. Until this issue is fixed, do not use these locations for the purposes indicated in the user guide.

This issue is fixed in version 14.0 of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.