Error(19732): Sector clock module_inst_0|clkctrl_0|clkena_inst drives to module_inst_1||data_in_reg[0] which is in a different partition. Sector clock gates and their destinations must be in the same partition.

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 22.2 and earlier, you may see this error during compilation on designs with Signal Tap enabled and an instance of the Clock Control FPGA IP. Currently, cross-partition sector gates are not supported.

Resolution

To work around this problem,  change the Clock Enable Type setting in the Clock Control FPGA IP parameter editor from Distributed Sector Level to Root Level and recompile.