CSR Address 0×05 and 0×06 Contents Cannot be Accessed

Description

Designs that use the high-performance controller II (HPC II) architecture with the Enable Configuration and Status Register Interface option turned on, cannot access the CSR address 0×05 and 0×06 contents.

This issue affects all designs that use the high-performance controller II architecture with the Enable Configuration and Status Register Interface option turned on.

Your design fails to simulate and doesn’t work in hardware.

Resolution

To access the CSR address 0×005 and 0×006 contents, perform the following steps:

1. Open <variation name>_controller_phy.v file.
2. Search for the following debug ports under the <variation name>_phy instantiation.

dbg_clk (Clock)

dbg_addr (Address)

dbg_cs (Chip select)

dbg_waitrequest (Wait request)

dbg_wr (Write request)

dbg_wr_data (Write data)

dbg_rd (Read request)

dbg_dr_data (Read data)

3. Export these ports into <variation name>_example.v file.
4. Use the Avalon-MM protocol to access the CSR address 0×005 and 0×006 contents through the debug ports.

This issue will not be fixed.