Avalon-ST interface VHDL BFM simulations fail in Riviera-PRO

Description

When simulating designs in the Aldec® Riviera-PRO™ Advanced Verification Platform, Avalon® Streaming (Avalon-ST) interface bus functional models (BFMs) fail with the following errors:

• Error: "# sim_run" not found in "log.txt". Simulation did not run.
• Error: Found 3 error(s) in "log.txt":

Error: 1211 | # ACOM: Error: ELAB1_0021: /build/arc/execute/dir_21768/_0/regtest/ip/merlin/altera_merlin_apb_slave_agent/sim_script/vhdl/riviera/top_tb/submodules/altera_avalon_st_sink_bfm_vhdl.vhd : (113, 0): Types do not match for port "data_in0". Error: 1212 | # ACOM: Error: ELAB1_0021: /build/arc/execute/dir_21768/_0/regtest/ip/merlin/altera_merlin_apb_slave_agent/sim_script/vhdl/riviera/top_tb/submodules/altera_avalon_st_sink_bfm_vhdl.vhd : (113, 0): Types do not match for port "data_out0". Error: 1214 | # SCRIPTER: Error: /build/arc/execute/dir_21768/_0/regtest/ip/merlin/altera_merlin_apb_slave_agent/sim_script/vhdl/riviera/aldec/rivierapro_setup.tcl : (222, 1): Script execution terminated due to error(s).

Resolution

This issue is fixed in Riviera-PRO version 2013.06 and the 13.1 Quartus® II software release.

To workaround this issue in the 13.0 Quartus II software release, you must edit your HDL code as follows (modifications in italics):

entity altera_avalon_interrupt_sink_vhdl is end altera_avalon_interrupt_sink_vhdl; architecture irq_sink_bfm_vhdl_a of altera_avalon_interrupt_sink_vhdl is -- component altera_avalon_interrupt_sink_vhdl_wrapper -- port ( data_out0 : out integer ); -- end component;

component altera_avalon_interrupt_sink_vhdl_wrapper port ( data_out0 : out std_logic_vector(0 to 31 ) ); end component; signal data_out0 : integer; function aldec_slv2int (val:std_logic_vector) return integer is begin return to_integer(unsigned(val)); end aldec_slv2int;

begin irq_sink_vhdl_wrapper : altera_avalon_interrupt_sink_vhdl_wrapper port map ( aldec_slv2int(data_out0) => data_out0 ); end irq_sink_bfm_vhdl_a;