10528 VHDL error at < component name>{}: Value “0” is outside the target constraint range (1 to 2147483647)

Description

This error may be seen during synthesis of Qsys systems generated VHDL due to a problem in the Quartus® II software version 13.0.   An incorrect data type “positive” is propagated by the HDL writer causing VHDL component declaration to be incompatible.

Resolution

To workaround this problem in the Quartus II software version 13.0:
- Choose Verilog for Synthesis in the Qsys GUI

Or

- Edit <component name>_hw.tcl  for the effected IP in a text editor, and change the parameter type from “positive” to integer”

This problem is currently scheduled to be fixed for a future version of the Quartus II Software.