New Contributor
New ContributorHallo again.
I have tried to eliminate all blanks but the error stay. I was suspicious and changed even the computername without a blank but it referes still to the old name, even after deinstalling an installing again.
Here is the Error text :Error (199013):..
Determining the location of the ModelSim executable...
Using: c:/intelfpga_lite/20.1/modelsim_ase/win32aloem/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LEDS -c LEDS --vector_source="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/output_files/Waveform1.vwf" --testbench_file="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/simulation/qsim/output_files/Waveform1.vwf.vht"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat May 21 07:32:12 2022
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LEDS -c LEDS --vector_source="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/output_files/Waveform1.vwf" --testbench_file="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/simulation/qsim/output_files/Waveform1.vwf.vht"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Error (199013): HDL output file name "C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/simulation/qsim/output_files/Waveform1.vwf.vht" used with --testbench_file option contains a non-existent directory path
Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 4711 megabytes
Error: Processing ended: Sat May 21 07:32:14 2022
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Error.
