New Contributor
New ContributorThank you. it worked, the spaces were the problems.
But I have a new Error. What does it mean?->
# ** Error (suppressible): (vsim-12110) The -novopt option has no effect on this product. -novopt option is now deprecated and will be removed in future releases.
# Error loading design
Error loading design
# End time: 11:13:26 on May 20,2022, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LEDS -c LEDS --vector_source="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/Waveform.vwf" --testbench_file="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/simulation/qsim/Waveform.vwf.vht"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Fri May 20 11:13:11 2022
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LEDS -c LEDS --vector_source="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/Waveform.vwf" --testbench_file="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/simulation/qsim/Waveform.vwf.vht"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/simulation/qsim/" LEDS -c LEDS
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Fri May 20 11:13:16 2022
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/simulation/qsim/" LEDS -c LEDS
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file LEDS.vho in folder "C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4715 megabytes
Info: Processing ended: Fri May 20 11:13:19 2022
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03
Completed successfully.
**** Generating the ModelSim .do script ****
C:/Users/Ilyas Cem KILIC/Desktop/VHDL/Projekt1/simulation/qsim/LEDS.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/intelfpga_lite/20.1/modelsim_ase/win32aloem//vsim -c -do LEDS.do
Reading pref.tcl
# 2020.1
# do LEDS.do
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 11:13:24 on May 20,2022
# vcom -work work LEDS.vho
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VITAL_Timing
# -- Loading package VITAL_Primitives
# -- Loading package dffeas_pack
# -- Loading package altera_primitives_components
# -- Loading package altera_lnsim_components
# -- Loading package cyclonev_atom_pack
# -- Loading package cyclonev_components
# -- Compiling entity LEDS
# -- Compiling architecture structure of LEDS
# End time: 11:13:24 on May 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 11:13:24 on May 20,2022
# vcom -work work Waveform.vwf.vht
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity LEDS_vhd_vec_tst
# -- Compiling architecture LEDS_arch of LEDS_vhd_vec_tst
# End time: 11:13:24 on May 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -novopt -c -t 1ps -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LEDS_vhd_vec_tst
# Start time: 11:13:25 on May 20,2022
# ** Error (suppressible): (vsim-12110) The -novopt option has no effect on this product. -novopt option is now deprecated and will be removed in future releases.
# Error loading design
Error loading design
# End time: 11:13:26 on May 20,2022, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
Error.
