Yet Another Verilog Inconvenience

Until VHDL2008 you couldn't create an array of unconstrained std_logic_vectors.

In AHDl you could specify a port with a double index, e.g. SQ[m..0][n..0] and have m and n parametrised by the caller. With VHDL1993 the best match was :

type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SQ : input 
->
SQ : in std_logic_2D(m downto 0, n downto 0);

Didn't look too kludgey to me ...

Using arrays of constrained std_logic_vectors requires the use of packages to declare the created type before it can be used in the port declaration, which is hardly a generic interface.

Wouldn't the SQ[m..0][n..0] in AHDL be correctly represented by

 wire  SQ 

or does that only work for 'reg'?

Anyway in QSys there is that strict notion of Symbols and Words which makes it impossible to have a ST-Source feed multiple datasets ( e.g. a std_logic_2D signal and a std_logic_vector signal) out to the next ST-Sink. Unless you start using multiple conduits and connect those in QSys as well. So I packed everything into a kludgey aggregated std_logic_vector and declared the symbol width equal to the size of that vector.