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Altera_Forum's avatar
Altera_Forum
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14 years ago

write_sdc is not working!

Check this out...I have a design with DDR3. I call the altera design constraints from timequest. Design passes timing. I then call write_sdc, reset my design, and read the 'written' sdc. The idea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Good find. Both the sdc and .tcl files used by report_ddr use the active clocks. My concern is that if you just remove them, they won't be analyzed at all. In reality, timing is met by taking their static timing analysis and then adding in what can recovered through calibration. So it's not that they're not analyzed at all, just that it's not a vanilla analysis.