Honored Contributor
Honored ContributorWhat takes so long is not the DDR3 constraints...they traverse the netlist only once in the fitter...altera does a good job of dumping the nets required to a database that is simply accessed on future runs. I think our issue is that our SDC files are not yet so slick. So we traverse the netlist with each call. However, I did figure out the issue. In one of the SDC files for the core, the following lines are used.
643 __if {(($::quartus(nameofexecutable) ne "quartus_fit") && ($::quartus(nameofexecutable) ne "quartus_map"))} {$ 644 ____set dqs_clocks [DDR3Memory_SIV_Cfg_1_Oct_Master_mem_if_ddr3_emif_0_p0_get_all_instances_dqs_pins DDR3Memory_SIV_Cfg_1_Oct_Master_mem_if_ddr3_emif_0_p0_ddr_db]$ 645 ____# Leave clocks active when in debug mode$ 646 ____if {[llength $dqs_clocks] > 0 && !$debug} {$ 647 ______post_sdc_message info "Setting DQS clocks as inactive; use Report DDR to timing analyze DQS clocks"$ 648 ______set_active_clocks [remove_from_collection [get_active_clocks] [get_clocks $dqs_clocks]]$ 649 ____}$ 650 __}$ Basically, when reporting timing in time quest, they do not have the failing paths set as active clocks. At this point I have all I need to work around the issue. Thanks for the hint... 'remove clocks'
