Don't use write_sdc for DDR3. (I don't like write_sdc for anything, and it really shouldn't save time, as it still needs to apply evey constraint to the .sdc. Heck, write_sdc usually creates more constriants).
The DDR3 is a dynamically calibrating core, which is generally not something that can be analyzed by "static timing analysis". A lot of special features are put into the .sdc and analysis .tcl scripts to handle this. For example, I know the .sdc creates some clocks and constrains them/analyzes them, but then removes the clock from analysis when TimeQuest is running. The reason is that paths in it will fail static timing analysis, yet work once calibration takes place. The report_ddr reports will have sections like "Before Calibration" which can have negative slack, but they don't show up in red unless they're still failing after calibration.
Anyway, the DDR3 analysis is not meant to work with that flow.