Why the type converter does not work ?

I define an new type which is an array:

type array_reg is array (C_NUM_REG-1 downto 0) of std_logic_vector (C_SLV_DWIDTH-1 downto 0);

Then I declare a signal:

signal slv_reg : array_reg;

slv_reg will be used as a group of registers whose number will be small, like 32, 64. Then I want to use input signal "slv_addr" as the address to reach the register. So I try to convert it to "slv_addr_integer " then use it as:

a<=slv_reg(slv_addr_integer);