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Bosenraum's avatar
Bosenraum
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7 years ago

Why does Qsys stop responding when generating DDR3 external memory interface?

I am trying to generate a design that is using the DDR3 SDRAM Controller with UniPHY IP core and during the Qsys HDL generation the generate window will hang rendering Qsys unusable. I am using Quart...
Bosenraum's avatar
Bosenraum
Icon for New Contributor rankNew Contributor
7 years ago

I am experiencing this on a few different projects and FPGAs. I should also mention that some of the designs I'm using were created (and successfully generated) by a coworker so this issue seems to be specific to me. I cannot even generate an example design for the memory controller IP through the Qsys megawizard. I'm wondering if this may be some sort of but related to this IP and Windows 10 but that is just speculation. If I remove this specific IP core I can use Qsys to generate just fine.