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Altera_Forum's avatar
Altera_Forum
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14 years ago

What's the purpose of set_clock_latency ?

We have a StratixIV design that if built 20 times with quartus, will fail 18 times when run on the board. Timing of the failing build is very similar to the timing of the "good" build. Th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Note that you can retime an image after changing the .sdc. For example, take one of the failing designs. After compiling, remove the set_clock_latency from the .sdc and run TimeQuest. Hopefully something pops up as failing, and you know what the issue is.