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Altera_Forum's avatar
Altera_Forum
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14 years ago

What's the purpose of set_clock_latency ?

We have a StratixIV design that if built 20 times with quartus, will fail 18 times when run on the board. Timing of the failing build is very similar to the timing of the "good" build. Th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

uclock and all generated clocks from it(and generated clocks from those generated clocks) will now have an extra 100ps delay. Anything analyzed between those clocks will not see it, since the 100ps will cancel out between the source clock and destination clock paths. But to other clocks not related, it will affect the setup and hold analysis by 100ps.

If the clock is delayed 100ps, then it's correct. If it's not, then it's not correct. Who put the constraint in?