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Altera_Forum
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14 years ago

What's the purpose of set_clock_latency ?

We have a StratixIV design that if built 20 times with quartus, will fail 18 times when run on the board. Timing of the failing build is very similar to the timing of the "good" build. Th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

What's the value of set_clock_latency? This command adds delay to the clock and can be used to model external clock delays. Unless multiple related clocks are coming into the FPGA, it only affects I/O timing, but it certainly will give a different result.

If the constraint is incorrect, then you're compiling with incorrect timing analysis and some of the time it may just happen to still pass. But the thing to investigate is if the analysis is correct.