What's the purpose of set_clock_latency ?

As far as I can understand it, "set_clock_latency -source" it's one way to model the delay between a clock source (ie, an oscillator) and the FPGA pin, when setting I/O delay constrains.

I've never used it, though. I just account for that delay into the I/O delay value.

My guess that it will affect timing for all I/Os based on that clock and derived clocks.

No clue on why it only causes problem's 20% of the time but if the design is at the limit... small things can make the difference.

If if were me, I'd try to redefine the I/O constrains without set_clock_latency.