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Altera_Forum's avatar
Altera_Forum
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12 years ago

What is mean by output port has no driver???

Hi,

I'm currently a final year student. Could anyone please help me to solve this problem. When i key in the verilog code, there are somes warning say that my output port has no driver. Can I know what is the meaning?

Here is my code.# ############################################################################################################

module FIR_interface(reset,clk,chipselect,writedata,readdata,x,selA,ld,Q);

input reset,clk,chipselect;

input [15:0]writedata,Q;

output [15:0]readdata;

output [7:0]x;

output ld;

output [2:0]selA;

reg [7:0]x;

reg [2:0]selA;

reg ld;

reg [15:0]readdata;

reg [3:0] c;

always @(posedge clk)

begin

if (reset==1)

readdata <=16'd0;

else if(chipselect)

begin

for(c=0;c<<4'd10;c=c+1)

begin

case (c)

(0|2|4|6|8) :

begin

x <= writedata[7:0];

selA <= writedata[10:8];

ld <= writedata[15];

end

(1|3|5|7|9) :

readdata[15:0] <= Q;

endcase

end

end

end

endmodule # ############################################################################################################

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    What are you hoping for from your 'for' loop? I suspect it is not doing what you want.

    Your code is instantiating 10 blocks of logic, one for each iteration of your for loop. However, it's not correct and, as I said, I suspect it's not what you want anyway.

    Give a brief description of what it is you're trying to do....
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I also it is wrong><

    actually this is the interface of my fir filter code.

    Here's my fir filter verilog..

    module toplvl (x,selA,clk,ld,rst,Q);

    input [7:0]x;

    input [2:0] selA;

    input clk,ld,rst;

    output [15:0] Q;

    wire [7:0] s1;

    wire [15:0] s2,s4;

    sel1 A1(selA,s1);

    multiplier A2(x,s1,s2);

    register A4(clk,ld,rst,s2,Q);

    endmodule

    module multiplier(x,b,p);

    input [7:0] x,b;

    output [15:0] p;

    assign p=x*b;

    endmodule

    module sel1(selA,b);

    input [2:0] selA;

    output [7:0] b;

    reg [7:0] b;

    always@*

    case(selA)

    0: b=8'd2;

    1: b=8'd4;

    2: b=8'd6;

    3: b=8'd8;

    4: b=8'd10;

    default: b=8'd0;

    endcase

    endmodule

    module register(clk,ld,rst,p,Q2);

    input clk,ld,rst;

    input [15:0] p;

    output [15:0] Q2;

    reg [15:0] Q2;

    always@(posedge clk)

    if (rst==1) Q2<=p;

    else if (ld==1)

    Q2=p+Q2;

    endmodule

    after that i hv to create an interface for it... cause I want to load it on DE2 board.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I don't know what you're asking for. This forum is for specific problems, which need specific questions...