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Honored Contributor
Honored ContributorWarnings in blackjack code
I am seeing the below warnings in my program for black jack and dont know how to fix it
WARNING:Xst:1780 - Signal <d_card6> is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal <d_card5> is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal <d_card4> is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:737 - Found 4-bit latch for signal <d_card1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <d_card2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <d_card3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <p_card3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <p_card4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <p_card5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 4-bit latch for signal <p_card6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 1-bit latch for signal <d_win>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 5-bit latch for signal <p_total>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 5-bit latch for signal <d_total>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 1-bit latch for signal <p_win>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 10-bit latch for signal <nextstate>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 1-bit latch for signal <d_win$mux0005>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 1-bit latch for signal <p_win$mux0005>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <d_win_mux0005>. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch <d_win_mux0005> (without init value) has a constant value of 0 in block <bjstate>. This FF/Latch will be trimmed during the optimization process. I have attached the code
