Warning Messages in conjunction with for PLLs

Hey, Carsten,

That means the source of the PLL's input clock is from a sub-optimal location or primitive. I'd guess you have a transceiver or serdes reference clock connected to a sub-optimal pin. It could also be that you're trying to use a PLL output clock to feed a PLL that's meant to be fed directly from a dedicated reference clk pin, or at least a suitable, nearby dedicated clk input pin.