Warning Messages in conjunction with for PLLs

Hello fpgaGuy,

there is only one kind of error message left. An explanation follows at the end of this thread.

Warning: PLL "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input

Info: Input port INCLK[0] of node "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" is driven by ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|clkctrl1

explanation:

FPGA: Cyclone IV E - EP4CE115F23I7

Deticated Input Clock Pin of the FPGA: Pin A12 = CLK8

-- First PLL

-------------

PLL2_inst : PLL2

PORT MAP (

areset => ResSys,

inclk0 => CLK, -- 50 MHz

c0 => Clk_50_E6_0_Pre, -- 50 MHz --> Clock Control Block

c1 => Clk_87_5_E6_0, -- 87,5 MHz

locked => PLL2_Locked

);

Clock Control Block

------------------

ClkCtrl_inst2 :

ClkCtrl PORT MAP ( inclk => Clk_50_E6_0_Pre,

outclk => Clk_50_E6_0

);

Second PLL

-----------

PLL1_inst : PLL

PORT MAP (

areset => PLL2_Locked,

inclk0 => Clk_50_E6_0, -- 50MHz

c0 => Clk_125_E6_180, -- 125 MHz/ 180°

c1 => Clk_125_E6_0, -- 125 MHz/ 0°

locked => PLL1_Locked

);

Third PLL

---------

PLL4_inst : PLL4

PORT MAP (

areset => PLL2_Locked,

inclk0 => Clk_50_E6_0, -- 50 MHz

c0 => Clk_64_166667_E6_0, -- 64,16667 MHz/ 0°

locked => PLL4_Locked

);

Any idea what`s the reason for the warning message?

BR,

Carsten