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Altera_Forum
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15 years ago

Warning Messages in conjunction with for PLLs

Hello together, for a new design i want to generate different clocks: 50 MHz intern 125 MHz intern 125 MHz extern 180° 87,5 MHz intern 66 MHz extern 64,167 MHz intern/extern ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

What are the interfaces or protocols at the I/O that are getting these warnings?

Please describe, preferably with a diagram, what your clocking architecture looks like. What is every element in the clocks' paths from pin, to PLL, to registers, RAMs, etc?