Honored Contributor
Honored ContributorHi Sean,
thank you for the hints. I don't want to merge PLLs. This is why I disable "Auto Merge PLLs" in the "Fitters Settings". With disabling this option, the are less warnings. But there are still two kinds of warnings: Type 1: -------- Warning: PLL "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input Info: Input port INCLK[0] of node "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" is driven by ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|clkctrl1 Type 2: ------- Warning: PLL "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" output port clk[0] feeds output pin "DviOClk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance Any ideas to remove this warnings?? Thank you Br, Carsten @fpgaGuy: I use the megafunction "ALTPLL".
