Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Warning Messages in conjunction with for PLLs

Hello together, for a new design i want to generate different clocks: 50 MHz intern 125 MHz intern 125 MHz extern 180° 87,5 MHz intern 66 MHz extern 64,167 MHz intern/extern ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

What MegaFunctions or MegaCores are you implementing that are trying to merge PLLs?

True LVDS resources have PLL restrictions per side (Left / Right). Are you using the LVDS Serdes/DPA?