Warning Messages in conjunction with for PLLs

Hi cchabrie,

I received the same error after I turned on a number of synthesis options recommended to me by the Optimization Advisor.

I think the trigger for it may be one of these synthesis options:

Perform WYSIWYG Primitive Resyntheis=ON

Remove Redundant Logic Cells=ON

Perform Register Duplication for Performance=OFF

These were OFF, OFF, and On respectively in my design and when I changed them I got this warning.

I don't think this warning is a problem because I think it is telling you it is trying to merge logic functions between two PLLs, but found parameters with each PLL that prevented them from being merged. If the PLLs have different parameters we wouldn't want them merged anyway...right?

-Sean