VMM using Questa.6.6.

Hi Dave,

How are you?

I am here again with a basic query in systemverilog interface. I have a testbench, in TOP module of this tb there is a binding of instance of interface with instance of modport of same interface.

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interface intf (input clock);

modeport mport();

endinterface

module my_module (intf.mport mport);

endmodule

module top;

intf interfc (clock);

my_module abc (.mport(interfc)); <== modeport's instance is binding with same interface's instance.... :confused:

endmodule

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I can't figure out why we need to pass interface this way. Is there any special reason or just a flexibility of code?

waiting for your reply.

Regards,

Dreku

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I don't think you'll find too many people using Questa on this forum.

Have you filed a service request with Mentor?

http://supportnet.mentor.com/

Their support is really very good.

Did you look to see where this function is defined in the VMM source?

Cheers,

Dave

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